IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 74

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
3.18.1.1.1
Master mode, the special feature in this mode is that the TSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked in by the TSCKn.
3.18.1.1.2
Master mode, the special feature in this mode is that the TSCKn is a
gapped 1.544 MHz clock (no clock signal during the selected channel).
‘1’. The TSCKn is also gapped during the channels or the Bit 8 duration
by selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a Don't Care condition.
3.18.1.2
1.544 Mb/s or 2.048 Mb/s. If the system data rate is 1.544 Mb/s, it works
in T1/J1 mode. If the system data rate is 2.048 Mb/s, the data stream to
be transmitted should be mapped to 1.544 Mb/s, that is, to work in T1/J1
2.048
1.544
Mb/s
Mb/s
2.048
1.544
Mb/s
Mb/s
Besides all the common functions described in the Transmit Clock
Besides all the common functions described in the Transmit Clock
The TSCKn is gapped during the F-bit if the FBITGAP bit is set to
In the Transmit Clock Slave mode, the system data rate can be
discarded
discarded
F
TS0
F
Transmit Clock Slave Mode
CH1
TS0
Transmit Clock Master Full T1/J1 Mode
Transmit Clock Master Fractional T1/J1 Mode
the 8th bit
CH1
TS1
TS1
Figure 25. E1 To T1/J1 Format Mapping - One Filler Every Four Channels Mode
CH2
CH2
TS2
TS2
CH3
TS3
Figure 24. E1 To T1/J1 Format Mapping - G.802 Mode
discarded
CH14
CH4
TS14 TS15 TS16 TS17 TS18
TS4
CH15
CH5
TS5
discarded
TS6
CH6
CH16
TS7
CH7
CH17
discarded
63
TS8
mode E1 rate. Three kinds of schemes are provided by selecting the
MAP[1:0] bits:
of Frame N on the system side are converted into Channel 1 to Channel
15 of Frame N to the device; TS17 to TS25 of Frame N on the system
side are converted into Channel 16 to Channel 24 of Frame N to the
device. The first bit of TS26 of Frame (N-1) on the system side is con-
verted into the F-bit of Frame N to the device. TS0, TS16, TS27~TS31
and the other 7 bits in TS26 on the system side are all discarded.
Figure 25): The 8th bit of Frame N on the system side is converted to the
F-bit of the Frame N to the device. Then one byte of the system side is
discarded after the previous three bytes are converted into the device.
This process repeats 8 times and the conversion of one frame is com-
pleted. Then the process goes on.
TS1 to TS24 of Frame N on the system side are converted into Channel
1 to Channel 24 of Frame N to the device. The 8th bit of Frame N on the
system side is converted into the F-bit of Frame N to the device. The first
7 bits and TS25 to TS31 on the system side are all discarded.
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
1. T1/J1 Mode E1 Rate per G.802 (refer to Figure 24): TS1 to TS15
2. T1/J1 Mode E1 Rate per One Filler Every Four CHs (refer to
3. T1/J1 Mode E1 Rate per Continuous CHs (refer to Figure 26):
TS9
CH23
CH22
TS24 TS25
discarded
TS28 TS29 TS30 TS31
CH24
the 1st bit
CH23
F
CH24
discarded discarded discarded
TS26 TS27~TS31
CH1
discarded
F
CH2
CH1
TS0
the 8th bit
CH2
March 22, 2004
TS0
TS1
CH23
TS1