IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 4

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
Table of Contents
3.9 PERFORMANCE MONITOR ........................................................................................................................................................................ 38
3.10 ALARM DETECTOR .................................................................................................................................................................................... 42
3.11 HDLC RECEIVER ......................................................................................................................................................................................... 45
3.12 BIT-ORIENTED MESSAGE RECEIVER (T1/J1 ONLY) .............................................................................................................................. 49
3.13 INBAND LOOPBACK CODE DETECTOR (T1/J1 ONLY) ........................................................................................................................... 49
3.14 ELASTIC STORE BUFFER .......................................................................................................................................................................... 50
3.15 RECEIVE CAS/RBS BUFFER ..................................................................................................................................................................... 50
3.16 RECEIVE PAYLOAD CONTROL ................................................................................................................................................................. 53
3.17 RECEIVE SYSTEM INTERFACE ................................................................................................................................................................. 55
3.18 TRANSMIT SYSTEM INTERFACE .............................................................................................................................................................. 62
3.9.1
3.9.2
3.10.1 T1/J1 Mode ...................................................................................................................................................................................... 42
3.10.2 E1 Mode .......................................................................................................................................................................................... 44
3.11.1 HDLC Channel Configuration ........................................................................................................................................................ 45
3.11.2 Two HDLC Modes ........................................................................................................................................................................... 45
3.15.1 T1/J1 Mode ...................................................................................................................................................................................... 50
3.15.2 E1 Mode .......................................................................................................................................................................................... 51
3.17.1 T1/J1 Mode ...................................................................................................................................................................................... 55
3.17.2 E1 Mode .......................................................................................................................................................................................... 60
3.18.1 T1/J1 Mode ...................................................................................................................................................................................... 62
3.18.2 E1 Mode .......................................................................................................................................................................................... 67
3.8.2.4
3.8.2.5
T1/J1 Mode ...................................................................................................................................................................................... 38
E1 Mode .......................................................................................................................................................................................... 40
3.11.2.1 HDLC Mode ...................................................................................................................................................................... 45
3.11.2.2 SS7 Mode ......................................................................................................................................................................... 47
3.17.1.1 Receive Clock Master Mode ............................................................................................................................................ 55
3.17.1.2 Receive Clock Slave Mode .............................................................................................................................................. 56
3.17.1.3 Receive Multiplexed Mode ............................................................................................................................................... 57
3.17.1.4 Offset ................................................................................................................................................................................ 57
3.17.1.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/MRSIGA(MRSIGB) .................................................................................. 59
3.17.2.1 Receive Clock Master Mode ............................................................................................................................................ 60
3.17.2.2 Receive Clock Slave Mode .............................................................................................................................................. 60
3.17.2.3 Receive Multiplexed Mode ............................................................................................................................................... 61
3.17.2.4 Offset ................................................................................................................................................................................ 61
3.17.2.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/MRSIGA(MRSIGB) .................................................................................. 61
3.18.1.1 Transmit Clock Master Mode ............................................................................................................................................ 62
3.18.1.2 Transmit Clock Slave Mode ............................................................................................................................................. 63
3.18.1.3 Transmit Multiplexed Mode .............................................................................................................................................. 64
3.18.1.4 Offset ................................................................................................................................................................................ 65
3.18.2.1 Transmit Clock Master Mode ............................................................................................................................................ 67
3.8.2.3.3
3.8.2.3.4
3.8.2.3.5
3.8.2.3.6
3.8.2.3.7
V5.2 Link .......................................................................................................................................................................... 36
Interrupt Summary ............................................................................................................................................................ 36
3.17.1.1.1 Receive Clock Master Full T1/J1 Mode ......................................................................................................... 55
3.17.1.1.2 Receive Clock Master Fractional T1/J1 Mode ............................................................................................... 56
3.17.2.1.1 Receive Clock Master Full E1 Mode ............................................................................................................. 60
3.17.2.1.2 Receive Clock Master Fractional E1 Mode ................................................................................................... 60
3.18.1.1.1 Transmit Clock Master Full T1/J1 Mode ........................................................................................................ 63
3.18.1.1.2 Transmit Clock Master Fractional T1/J1 Mode .............................................................................................. 63
3.18.2.1.1 Transmit Clock Master Full E1 Mode ............................................................................................................ 67
3.18.2.1.2 Transmit Clock Master Fractional E1 Mode .................................................................................................. 67
National Bit Extraction ................................................................................................................................... 35
National Bit Codeword Extraction .................................................................................................................. 35
Extra Bit Extraction ........................................................................................................................................ 35
Remote Signaling Multi-Frame Alarm Indication Bit Extraction ..................................................................... 35
Sa6 Code Detection Per ETS 300 233 .......................................................................................................... 35
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OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
March 22, 2004