IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 86

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
3.20.2
form HDLC or SS7 packet data stream.
3.20.2.1
(#1, #2 & #3) per link are provided for HDLC insertion to the data stream
to be transmitted. In T1/J1 mode SF & SLC-96 formats, two HDLC
Transmitters (#2 & #3) per link are provided for HDLC insertion. In E1
mode, three HDLC Transmitters (#1, #2 & #3) per link are provided for
HDLC insertion. Except in T1/J1 mode ESF & T1 DM formats, the HDLC
channel of HDLC Transmitter #1 is fixed in the DL bit (in ESF format)
and D bit in CH24 (in T1 DM format) respectively (refer to Table 13 &
Table 14), the other HDLC channel is configured as the follows:
odd frames;
assigned frame;
timeslot.
if the corresponding TDLEN bit is set to ‘1’.
Table 51: Related Bit / Register In Chapter 3.20.2.1
BITEN[7:0]
TDLEN3
TDLEN2
TDLEN1
TS[4:0]
EVEN
ODD
The HDLC Transmitter inserts the data into the selected position to
In T1/J1 mode ESF & T1 DM formats, three HDLC Transmitters
1. Set the EVEN bit and/or the ODD bit to select the even and/or
2. Set the TS[4:0] bits to define the channel/timeslot of the
3. Set the BITEN[7:0] bits to select the bits of the assigned channel/
Then all the functions of the HDLC Transmitter will be enabled only
Bit
HDLC TRANSMITTER
ment / THDLC3 Assignment
HDLC Channel Configuration
only) / THDLC2 Bit Select /
THDLC1 Assignment (E1
only) / THDLC2 Assign-
THDLC1 Bit Select (E1
THDLC Enable Control
THDLC3 Bit Select
Register
085, 185, 285, 385, 485, 585, 685,
785 (E1 only) / 086, 186, 286, 386,
088, 188, 288, 388, 488, 588, 688,
788 (E1 only) / 089, 189, 289, 389,
084, 184, 284, 384, 484, 584, 684,
489, 589, 689, 789 / 08A, 18A,
28A, 38A, 48A, 58A, 68A, 78A
486, 586, 686, 786 / 087, 187,
287, 387, 487, 587, 687, 787
Address (Hex)
784
75
3.20.2.2
ter. The two modes are: HDLC mode (per Q.921) and SS7 (per Q.703).
3.20.2.2.1
DAT[7:0] bits. The FIFO depth is 128 bytes. When it is full, it will be indi-
cated by the FUL bit. When it is empty, it will be indicated by the EMP bit.
EOM bit, or if the data in the FIFO exceeds the upper threshold set by
the HL[1:0] bits, the data in the FIFO will be transmitted. The opening
flag (‘01111110’) will be prepended before the data automatically. The
transmission will not stop until the entire HDLC data are transmitted.
Then the 2-byte FCS and the closing flag (‘01111110’) will be added to
the end of the HDLC data automatically. During the HDLC data trans-
mission, a zero is stuffed automatically into the serial output data if there
are five consecutive ’One’s ahead.
packet anytime when the ABORT bit is set. Or when the FIFO is empty
and the transmitted last byte is not the end of the current HDLC packet,
the abort sequence will be transmitted automatically.
FIFO to be transmitted, the 7E (Hex) flag will always be transmitted.
3.20.2.2.2
bits. The FIFO depth is 128 bytes. When it is full, it will be indicated by
the FUL bit. When it is empty, it will be indicated by the EMP bit.
bit, or if the data in the FIFO exceeds the upper threshold set by the
HL[1:0] bits, the data in the FIFO will be transmitted. The opening flag
(‘01111110’) will be prepended before the data automatically. The trans-
mission will not stop until the entire SS7 data are transmitted. Then the
2-byte FCS and the closing flag (‘01111110’) will be added to the end of
the SS7 data automatically. During the SS7 data transmission, a zero is
stuffed automatically into the serial output data if there are five consecu-
tive ’One’s ahead.
anytime when the ABORT bit is set. Or when the FIFO is empty and the
last transmitted byte is not the end of the current SS7 packet, the abort
sequence will be transmitted automatically.
FIFO and the XREP bit is set to ‘1’, these bytes in the FIFO will be trans-
mitted repeatedly with the opening flag, FCS and closing flag, until the
XREP bit is disabled and the current packet transmission is finished.
However, during the cyclic transmission period, the data written into the
FIFO will not be transmitted.
transmitted, the 7E (Hex) flags will be transmitted N times (the ‘N’ is
determined by the FL[1:0] bits), then the FISU packet will be transmitted
(refer to Figure 14) with the BSN and FSN the same as the last transmit-
ted packet.
to be transmitted, the 7E (Hex) flag will always be transmitted.
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Two modes are selected by the THDLCM bit in the HDLC Transmit-
A FIFO buffer is used to store the HDLC data written in the
If an entire HDLC packet is stored in the FIFO indicated by the
The abort sequence (‘01111111’) will be inserted to the HDLC
If the TDLEN bit is enabled and there is no HDLC packet in the
A FIFO buffer is used to store the SS7 data written in the DAT[7:0]
If an entire SS7 packet is stored in the FIFO indicated by the EOM
The abort sequence (‘01111111’) will be inserted to the SS7 packet
When the FIFO is empty, if less than 16 bytes are written into the
If the AUTOFISU bit is set and there is no data in the FIFO to be
If the TDLEN bit is enabled and there is no SS7 packet in the FIFO
Two HDLC Modes
HDLC Mode
SS7 Mode
March 22, 2004