GS1559-CBE2 Gennum Corp., GS1559-CBE2 Datasheet - Page 61

• Manufacturer Part Number: GS1559-CBE2
• Description: HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver
• Manufacturer: Gennum Corp.

4.11.1 Parallel Data Bus Buffers
The parallel data outputs of the GS1559 are driven by high-impedance buffers
which support both LVTTL and LVCMOS levels. These buffers use a separate
power supply of +3.3V DC supplied via the IO_VDD and IO_GND pins.
All output buffers, including the PCLK output, may be driven to a high-impedance
state if the RESET_TRST signal is asserted LOW.
Note that the timing characteristics of the parallel data output buffers are optimized
for 10-bit HD operation. As shown in
is 1.5ns.
Due to this optimization, however, the output data hold time for SD data is so small
that the rising edge of the PCLK is nearly incident with the data transition. To
improve output hold time at SD rates, the PCLK output is inverted is SD mode,
(SD/HD = HIGH). This is shown in
Control signal
Figure 4-7: HD PCLK to Data Timing
Figure 4-8: SD PCLK to Data Timing
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Control signal
DOUT[19:0]
DOUT[19:0]
output
output
PCLK
PCLK
SD MODE
DATA
30572 - 1
HD MODE
DATA
t
OH
t
OD
Figure
Figure
t
OH
GS1559 Preliminary Data Sheet
t
November 2004
OD
4-8.
4-7, the output data hold time for HD
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