GS1559-CBE2 Gennum Corp., GS1559-CBE2 Datasheet - Page 66

• Manufacturer Part Number: GS1559-CBE2
• Description: HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver
• Manufacturer: Gennum Corp.

4.12.3 Configuration and Status Registers
4.13 JTAG
Table 4-17
All of these registers are available to the host via the GSPI and are all individually
addressable.
Where status registers contain less than the full 16 bits of information however, two
or more registers may be combined at a single logical address.
Table 4-17: GS1559 internal registers
When the JTAG/HOST input pin of the GS1559 is set HIGH, the host interface port
will be configured for JTAG test operation. In this mode, pins H4 to H6 and J6
become TMS, TCK, TDO, and TDI. In addition, the RESET_TRST pin will operate
as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS1559:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other
devices driving the digital I/O pins. If the tests are to be applied only at ATE, this
can be accomplished with tri-state buffers used in conjunction with the
JTAG/HOST input signal. This is shown in
Proprietary and Confidential
Address
000h
001h
003h
004h
005h - 009h
00Ch - 00Dh
00Eh - 011h
012h - 019h
01Ah
Equipment) during PCB assembly; or
summarizes the GS1559's internal status and configuration registers.
Register Name
IOPROC_DISABLE
ERROR_STATUS
EDH_FLAG
VIDEO_STANDARD
ANC_TYPE
VIDEO_FORMAT
RASTER_STRUCTURE
EDH_CALC_RANGES
ERROR_MASK
30572 - 1
GS1559 Preliminary Data Sheet
November 2004
Figure
4-14.
See Section
Section 4.10.6
Section 4.10.5
Section 4.10.7
Section 4.10.4
Section 4.10.2.1
Section 4.10.3
Section 4.10.4
Section 4.10.5.2
Section 4.10.5
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