S2042 AMCC (Applied Micro Circuits Corp), S2042 Datasheet - Page 14

• Manufacturer Part Number: S2042
• Description: High Performance Serial Interface Circuits
• Manufacturer: AMCC (Applied Micro Circuits Corp)

14
S2042/S2043
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels (.8V or
Table 6. S2043 Receiver Timing
T
T
Parameters
Duty Cycle
Input Jitter
RCR ,
T
SDR ,
Tolerance
DR ,
T
LOCK
T
T
T
T
T
2.0V). All TTL AC measurements are assumed to have the output load of 10pF.
3
4
5
6
7
Table 5. AC Characteristics
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output
T
T
T
Transmitter Output Jitter Allocation
T
RCF
DF
SDF
Parameters
T
SDR ,
CR ,
T
T
J RMS
T
T
T
T
T
T
T
DC
DJ
1
2
3
4
5
6
data levels (.8V or 2.0V). All TTL AC measurements are assumed to have the output load of 10pF.
T
T
CF
SDF
RCLK to RCLKN skew
Data set-up time
Data hold time
Data set-up time
Data hold time
RCLK rise and fall time
Data Output rise and fall time
Serial data input rise and fall
Data acquisition lock time @
<1.0625Gb/s
RCLK/RCLKN Duty Cycle
Input data eye opening
allocation at receiver input
for BER 1E–12
Description
Serial data output
deterministic jitter (p-p)
REFCLK to TCLK
Data setup w.r.t. REFCLK
Data hold w.r.t. REFCLK
Data setup w.r.t. TCLK
Data hold w.r.t. TCLK
TCLK rise and fall time
Serial data rise and fall
TCLK to TCLKN Skew
TCLK, TCLKN Duty Cycle
Serial data output random
jitter (RMS)
Description
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
40%
30%
Min
3.0
1.5
2.5
7.5
—
—
—
—
—
Min
1.0
1.0
2.0
40
—
—
—
—
—
5
1
60%
300
100
4.0
5.0
300
Max
60
20
—
—
5.0
5.0
2.4
Max
1
—
—
—
—
—
1
Units
ns
ns
ns
ns
ns
ns
ps
ns
ps
ps
%
bit time
Units
6195 Lusk Blvd., San Diego, CA 92121 • [phone]
ns
ns
ns
ns
ns
ns
ns
ps
s
10% to 90%, tested on a sample basis.
20% to 80%, tested on a sample basis.
Tested on a sample basis.
RMS, tested on a sample basis.
Measured with 1010 pattern.
Peak-to-peak, tested on a sample basis.
Measured with IDLE pattern.
Tested on a sample basis.
1062 Mbit/sec, 10-bit mode.
1062 Mbit/sec, 10-bit mode.
1062, 531 Mbit/sec, 20-bit mode.
531, 266 Mbit/sec, 20-bit mode.
1062, 531 Mbit/sec, 20-bit mode.
531, 266 Mbit/sec, 20-bit mode.
10% to 90%, tested on a sample basis.
10% to 90%, tested on a sample basis.
20% to 80%.
8B/10B IDLE pattern sample basis
As specified in Fibre Channel FC–PH
standard eye diagram jitter mask.
Conditions
—
—
—
—
Applied Micro Circuits Corporation
Conditions