S2050 AMCC (Applied Micro Circuits Corp), S2050 Datasheet - Page 2

• Manufacturer Part Number: S2050
• Description: Bicmos Pecl Clock Gigabit Ethernet Chipset
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S2046/S2050 OVERVIEW
The S2046 transmitter and S2050 receiver provide
serialization and deserialization functions for block-
encoded data to implement a Gigabit interface.
Operation of the S2046/S2050 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
Transmitter
Receiver
The 10/20-bit parallel data handled by the S2046 and
S2050 devices should be from a DC-balanced en-
coding scheme, such as the 8B/10B transmission
code, in which information to be transmitted is en-
coded 8 bits at a time into 10-bit transmission
characters.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 5.
A lock detect feature is provided on the receiver,
which indicates that the PLL is locked (synchronized)
to the data stream.
Figure 3. S2046 Functional Block Diagram
2
S2046/S2050
1. 10/20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10/20-bit parallel output
REFCLK
REFSEL
D[19:0]
TEST
DWS
OE0
OE1
20
D
CONTROL
Q
LOGIC
F 0 = F 1 X 10/20
10
10
MULTIPLIER
PLL CLOCK
2:1
10
REGISTER
SHIFT
DIVIDE-BY-2
Loopback
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
Figure 2. Interface Diagram
S2046 TRANSMITTER
Architecture/Functional Description
The S2046 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The S2046 is fully compliant with the
proposed 802.3z Specification, and supports the Gi-
gabit Ethernet data rate of 1250 Mbps.
Parallel
Data In
REFCLK
TCLKN
TCLK
Transmitter
S2046
GIGABIT ETHERNET CHIPSET
Loopback
TX/Y
TLX/Y
Serial
Data
Loopback
RLX/Y
March 29, 2000 / Revision B
RX/Y
Receiver
S2050
LOCKDETN
TX
TY
TLX
TLY
TCLK
TCLKN
RCLK
RCLKN
SYNC
REFCLK
Parallel
Data Out