S2052 AMCC (Applied Micro Circuits Corp), S2052 Datasheet - Page 12

• Manufacturer Part Number: S2052
• Description: Bicmos Pecl Clock Generator Fibre Channel And Gigabit Ethernet Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

12
S2052
Table 5. S2052 Receiver Timing
Note: All TTL/CMOS AC measurements are assumed to have the output load of 10pF.
T
T
Parameters
Table 4. S2052 Transmitter Timing
Duty Cycle
Input Jitter
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels
(.8V or 2.0V).
RCR ,
T
SDR ,
Tolerance
Transmitter Output Jitter Allocation
T
DR ,
Parameters
T
SDR ,
LOCK
T
T
T
T
T
3
4
5
6
7
T
T
T
T
T
T
T
DJ
1
2
J
RCF
DF
SDF
T
SDF
RBC0 to RBC1 skew
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
RBC0, RBC1 rise and fall time
Data Output rise and fall time
Serial data input rise and fall
Data acquisition lock time @
<1.0625Gb/s
RBC0/RBC1 Duty Cycle
Input data eye opening
allocation at receiver input
for BER 1E–12
Serial data output
deterministic jitter (p-p)
Data setup w.r.t.
Data hold w.r.t.
Serial data rise and fall
Serial data output total
jitter (RMS)
Description
Description
Table 3. S2052 Performance Summary
*
Operating Frequency *
Serial clock period
Byte clock period
Acquisition Time
Reference clock
Word width
10% lock range, nominal frequency is per FC-PH standard.
REFCLK
Parameter
REFCLK
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
40%
24%
Min
3.0
1.5
2.5
1.5
Min
1.0
—
—
—
—
—
—
—
—
2
125.0
1250
60%
300
.800
8.00
300
192
3.0
3.0
2.4
250
Max
80
Max
—
—
—
10
1
S2052
bit time
Units
Units
ns
ns
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ps
1062.5
106.25
s
.941
9.41
250
10
20% to 80%, tested on a sample basis.
Peak-to-peak, tested on a sample basis.
Measured with
Peak-to-peak, tested on a sample basis.
Measured with K28.5 @ 1.25 GHz.
Tested on a sample basis.
1.0625 GHz Mode
1.0625 GHz Mode
1.250 GHz Mode
1.250 GHz Mode
Measured from .8V to 2.0V.
Measured from .8V to 2.0V.
20% to 80%. (See Figure 10.)
8B/10B IDLE pattern sample basis.
As specified in IEEE 803.3z.
Units
Mbit/s
MHz
Bits
ns
ns
ns
See note.
Conditions
Conditions
—
K28.5 or 2
April 29, 1999 / Revision E
7
-1 pattern.