S2062 AMCC (Applied Micro Circuits Corp), S2062 Datasheet - Page 7

• Manufacturer Part Number: S2062
• Description: Dual Serial Backplane Device
• Manufacturer: AMCC (Applied Micro Circuits Corp)

June 20, 2000 / Revision B
A special input, SOF, is provided for each channel to
simplify the generation of the K28.5 character. When
SOF is asserted, the K28.5 character is generated
regardless of the data on the parallel input. The K28.5
character can be of either positive or negative parity,
depending on the current running disparity. Table 4
shows the mapping of the 8B/10B characters repre-
sentation. Data is transmitted bit “a” or DIN[0] first.
In addition to data and K characters, the S2062 can
also generate a unique sync sequence consisting of
16 consecutive K28.5 characters. This event is initi-
ated by the simultaneous assertion of KGENx and
SOFx for one clock period. The SOFx and KGENx
inputs should be held low until the sync sequence has
completed. The sync sequence may start with either a
positive or negative parity K28.5. (Depending on the
current running disparity.) The parity of the second
and third K28.5 are inverse with respect to a valid 8B/
Table 1. Input Modes
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
Figure 6. DIN Data Clocking with TCLK
DUAL SERIAL BACKPLANE DEVICE
T
M
O
0
1
D
E
ASIC
MAC
R
c
c
T
d
o l
h
a
B
E
a
a t
k c
C
F
n
C
n
n i
M
d
L
e
o t
a
o
K
. s l
a t
d
F
M
. e
F I
n i
o
T
O
o t
d
O
B
. e
p
s
C
F
r e
f
R
F I
x
r o
TCLKO
DINx[0:7]
TCLKx
t a
E
u
O
VCO/10 or VCO/20
o i
F
l a
s
s
OSCILLATOR
e
C
c l
S2062
n
f
d
REFCLK
L
r o
PLL
REF
h
K
o t
a
l l a
u
n
c
s
n
o l
e
e
k c
d
. s l
o t
Table 2. Transmitter Control Signals
10B sequence. Parity of the remaining K28.5 alter-
nate in accordance with the 8B/10B coding standard.
Thus, the parity of the K28.5 pattern consists of + + - -
+ - + - + - + - + - + - or - - + + - + - + - + - + - + - +.
Table 2 shows the transmitter control signals.
Frequency Synthesizer (PLL)
The S2062 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2062 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
1
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
Figure 7. DIN Clocking with REFCLK
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
S
O
0
0
1
1
F
x
K
ASIC
MAC
G
E
0
1
0
1
N
x
E
K
3
K
S
+
- -
n
2
p
a
+
C
c
8
e
+
n
h
o
5 .
c
- -
d
+
d
a
l a i
a r
e
I D
C
+
-
S
d
1
h
t c
+
[ N
-
2
6
a
P
r e
+
-
0
a r
: 7
r a
w
6
+
-
TCLKO
t c
a
] 0
o
DINx[0:7]
TCLKx
2
l a
+
-
s
d r
r e
D
l e l
+
-
d
OSCILLATOR
N I
c
f e
+
-
D
h
S2062
REFCLK
+
n i
VC0/10
-
a
O
a
REF
PLL
a r
+
-
a t
e
u
d
+
c
p t
-
e t
b
+
-
t u
y
+
, r
-
S2062
T
r o
a
b
e l
7