USB3280 SMSC Corporation, USB3280 Datasheet - Page 23

• Manufacturer Part Number: USB3280
• Description: Hi-Speed USB Device PHY
• Manufacturer: SMSC Corporation

Hi-Speed USB Device PHY with UTMI Interface
Datasheet
SMSC USB3280
7.5
RX Logic
The behavior of the Transmit State Machine is described below.
This block receives serial data from the CRC block and processes it to be transferred to the SIE on
the DATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial to parallel
conversion. Upon valid assertion of the proper RX control lines by the RX State Machine, the RX Logic
block will provide bytes to the DATA bus as shown in the figures below. The behavior of the Receive
State Machine is described below.
The assertion of RESET will force the Receive State Machine into the Reset state. The Reset state
deasserts RXACTIVE and RXVALID. When the RESET signal is deasserted the Receive State
Machine enters the RX Wait state and starts looking for a SYNC pattern on the USB. When a SYNC
pattern is detected the state machine will enter the Strip SYNC state and assert RXACTIVE. The length
of the received Hi-Speed SYNC pattern varies and can be up to 32 bits long or as short as 12 bits
long when at the end of five hubs. As a result, the state machine may remain in the Strip SYNC state
for several byte times before capturing the first byte of data and entering the RX Data state.
After valid serial data is received, the state machine enters the RX Data state, where the data is loaded
into the RX Holding Register on the rising edge of CLKOUT and RXVALID is asserted. The SIE must
clock the data off the DATA bus on the next rising edge of CLKOUT. If OPMODE = Normal, then
stuffed bits are stripped from the data stream. Each time 8 stuffed bits are accumulated the state
machine will enter the RX Data Wait state, negating RXVALID thus skipping a byte time.
Asserting a RESET forces the transmit state machine into the Reset state which negates
TXREADY. When RESET is negated the transmit state machine will enter a wait state.
The SIE asserts TXVALID to begin a transmission.
After the SIE asserts TXVALID it can assume that the transmission has started when it detects
TXREADY has been asserted.
The SIE must assume that the USB3280 has consumed a data byte if TXREADY and TXVALID
are asserted on the rising edge of CLKOUT.
The SIE must have valid packet information (PID) asserted on the DATA bus coincident with the
assertion of TXVALID.
TXREADY is sampled by the SIE on the rising edge of CLKOUT.
The SIE negates TXVALID to complete a packet. Once negated, the transmit logic will never
reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until
TXVALD asserts again.
The USB3280 is ready to transmit another packet immediately, however the SIE must conform to
the minimum inter-packet delays identified in the USB 2.0 specification.
Figure 7.4 Receive Timing for Data with Unstuffed Bits
DATASHEET
23
Revision 1.2 (10-27-06)