AD9516-1 Analog Devices, AD9516-1 Datasheet

AD9516-1

Manufacturer Part Number

AD9516-1

Description

14-Output Clock Generator

Manufacturer

Analog Devices

Datasheet

1.AD9516-1.pdf (84 pages)

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FEATURES

Low phase noise, phase-locked loop

3 pairs of 1.6 GHz LVPECL outputs

2 pairs of 800 MHz LVDS clock outputs

Eight 250 MHz CMOS outputs (two per LVDS output)

Automatic synchronization of all outputs on power-up

Manual synchronization of outputs as needed

Serial control port

64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

ATE

GENERAL DESCRIPTION

The AD9516-1

function with subpicosecond jitter performance, along with an on-

chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to

2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz

may be used.

The AD9516-1 emphasizes low jitter and phase noise to

maximize data converter performance and can benefit other

applications with demanding phase noise and jitter requirements.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

On-chip VCO tunes from 2.30 GHz to 2.65 GHz

External VCO/VCXO to 2.4 GHz optional

One differential or two single-ended reference inputs

Reference monitoring capability

Auto and manual reference switchover/holdover modes

Autorecover from holdover

Accepts references to 250 MHz

Programmable delays in path to PFD

Digital or analog lock detect, selectable

Each pair shares 1 to 32 dividers with coarse phase delay

Additive output jitter 225 f

Channel-to-channel skew paired outputs <10 ps

Each pair shares two cascaded 1 to 32 dividers with coarse

Additive output jitter 275 f

Fine delay adjust (ΔT) on each LVDS output

phase delay

provides a multi-output clock distribution

rms

14-Output Clock Generator with

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

The AD9516-1 features six LVPECL outputs (in three pairs);

four LVDS outputs (in two pairs); and eight CMOS outputs

(two per LVDS output). The LVPECL outputs operate to

1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS

outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide

ratio and coarse delay (or phase) to be set. The range of division

for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs

allow a range of divisions up to a maximum of 1024.

The AD9516-1 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated

by connecting the charge pump supply (VCP) to 5.5 V. A

separate LVPECL power supply can be from 2.375 V to 3.6 V.

The AD9516-1 is specified for operation over the industrial

range of −40°C to +85°C.

AD9516 is used throughout to refer to all the members of the AD9516

family. However, when AD9516-1 is used, it is referring to that specific

member of the AD9516 family.

REFIN

CLK

FUNCTIONAL BLOCK DIAGRAM

SERIAL CONTROL PORT

Integrated 2.5 GHz VCO

DIV/Φ

REF1

REF2

DIGITAL LOGIC

AND

AND MUXs

DIVIDER

DIV/Φ

Figure 1.

ΔT

LVPECL

LVDS/CMOS

VCO

AD9516-1

MONITOR

STATUS

www.analog.com

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

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