AD9516-1 Analog Devices, AD9516-1 Datasheet - Page 44

• Manufacturer Part Number: AD9516-1
• Description: 14-Output Clock Generator
• Manufacturer: Analog Devices

Divider
0
1
2
AD9516-1
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 38).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset, or delay, the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by 5 bits
loaded into the phase offset (PO) register plus the start high
(SH) bit for each channel divider. When the start high bit is set,
the delay is also affected by the number of low cycles (M)
programmed for the divider.
It is necessary to use the SYNC function to make phase offsets
effective (See the Synchronizing the Outputs—SYNC Function
section).
Table 38. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 2
Let
Δ
Δ
T
(in seconds).
Φ =
16 × SH<4> + 8 × PO<3> + 4 × PO<2> + 2 × PO<1> + 1 × PO<0>
The channel divide-by is set as N = high cycles and M = low cycles.
Case 1
For Φ ≤ 15:
Δ
Δ
Case 2
For Φ ≥ 16:
Δ
Δ
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 53 shows the results of setting such a coarse
offset between outputs.
t
c
X
t
c
t
c
= delay (in seconds).
= Φ × T
= (Φ − 16 + M + 1) × T
= delay (in cycles of clock signal at input to D
= Δ
= Δ
= period of the clock signal at the input of the divider, D
t
t
/T
/T
X
X
Start
High (SH)
0x191<4>
0x194<4>
0x197<4>
X
= Φ
Phase
Offset (PO)
0x191<3:0>
0x194<3:0>
0x197<3:0>
X
Low Cycles
M
0x190<7:4>
0x193<7:4>
0x196<7:4>
X
).
High Cycles
N
0x190<3:0>
0x193<3:0>
0x196<3:0>
X
Rev. 0 | Page 44 of 84
DIVIDER 0
DIVIDER 1
DIVIDER 2
Channel Dividers—LVDS/CMOS Outputs
Channel Divider 3 and Channel Divider 4 each drive a pair of
LVDS outputs, giving a total of four LVDS outputs (OUT6 to
OUT9). Alternatively, each of these LVDS differential outputs
can be configured individually as a pair (A and B) of CMOS
single-ended outputs, providing for up to eight CMOS outputs.
By default, the B output of each pair is off but can be turned on
as desired.
Channel Divider 3 and Channel Divider 4 each consist of two
cascaded, 1 to 32, frequency dividers. The channel frequency
division is D
have DCC enabled by default, but this function can be disabled,
if desired, by setting the DCCOFF bit of the channel. A coarse
phase offset or delay is also programmable (see the Phase Offset
or Coarse Time Delay (Divider 3 and Divider 4) section). The
channel dividers operate up to 1600 MHz. The features and
settings of the dividers are selected by programming the
appropriate setup and control registers (see Table 51 and Table 52
through Table 61).
Table 39. Setting Division (D
Divider
3
4
Channel Frequency Division (Divider 3 and Divider 4)
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2).
When both X.1 and X.2 are bypassed, D
When only X.2 is bypassed, D
When both X.1 and X.2 are not bypassed, D
(N
DIVIDER INPUT
X.2
CHANNEL
Number of Low Cycles = M
Number of High Cycles = N
3.1
3.2
4.1
4.2
+ M
PO = 0
PO = 1
PO = 2
SH = 0
SH = 0
SH = 0
X.2
M
0x199<7:4>
0x19B<7:4>
0x19E<7:4>
0x1A0<7:4>
Figure 53. Effect of Coarse Phase Offset (or Delay)
+ 2).
X.1
× D
0
1
X.2
Tx
2
or up to 1024. Both of the dividers also
3
N
0x199<3:0>
0x19B<3:0>
0x19E<3:0>
0x1A0<3:0>
1 × Tx
2 × Tx
4
X
5
X
) for Divider 3, Divider 4
= (N
X.Y
X.Y
6
+ 1
+ 1
7
X.1
+ M
8
X
Bypass
0x19C<4>
0x19C<5>
0x1A1<4>
0x1A1<5>
= 1 × 1 = 1.
9 10 11 12 13 14 15
X
X.1
= (N
+ 2) × 1.
X.1
+ M
DCCOFF
0x19D<0>
0x19D<0>
0x1A2<0>
0x1A2<0>
X.1
+ 2) ×