AD9516-1 Analog Devices, AD9516-1 Datasheet - Page 76

• Manufacturer Part Number: AD9516-1
• Description: 14-Output Clock Generator
• Manufacturer: Analog Devices

Reg.
Addr
(Hex) Bit(s) Name
198
198
Reg.
Addr
(Hex) Bit(s)
199
199
19A
19A
19B
19B
19C
19C
19C
19C
19C
19C
19D
19E
19E
19F
19F
1A0
1A0
AD9516-1
Table 58. LVDS/CMOS Channel Dividers
<1>
<0>
<7:4> Low Cycles Divider 3.1
<3:0> High Cycles Divider 3.1
<7:4> Phase Offset Divider 3.2
<3:0> Phase Offset Divider 3.1
<7:4> Low Cycles Divider 3.2
<3:0> High Cycles Divider 3.2
<5>
<4>
<3>
<2>
<1>
<0>
<0>
<7:4> Low Cycles Divider 4.1
<3:0> High Cycles Divider 4.1
<7:4> Phase Offset Divider 4.2
<3:0> Phase Offset Divider 4.1
<7:4> Low Cycles Divider 4.2
<3:0> High Cycles Divider 4.2
Divider 2 Direct to Output
Divider 2 DCCOFF
Name
Bypass Divider 3.2
Bypass Divider 3.1
Divider 3 Nosync
Divider 3 Force High
Start High Divider 3.2
Start High Divider 3.1
Divider 3 DCCOFF
Description
Connect OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
<1> = 0; OUT4 and OUT5 are connected to Divider 2.
<1> = 1:
If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT4 and OUT5.
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT4 and OUT5.
If 0x1E1<1:0> = 01b, there is no effect.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Description
Number of clock cycles of 3.1 divider input during which 3.1 output stays low.
Number of clock cycles of 3.1 divider input during which 3.1 output stays high.
Refer to LVDSCMOS channel divider function description.
Refer to LVDSCMOS channel divider function description.
Number of clock cycles of 3.2 divider input during which 3.2 output stays low.
Number of clock cycles of 3.2 divider input during which 3.2 output stays high.
Bypass (and power-down) 3.2 divider logic, route clock to 3.2 output.
<5> = 0; do not bypass.
<5> = 1; bypass.
Bypass (and power-down) 3.1 divider logic, route clock to 3.1 output.
<4> = 0; do not bypass.
<4> = 1; bypass.
Nosync.
<3> = 0; obey chip-level SYNC signal.
<3> = 1; ignore chip-level SYNC signal.
Force Divider 3 output high. Requires that nosync also be set.
<2> = 0; force low.
<2> = 1; force high.
Divider 3.2 start high/low.
<1> = 0; start low.
<1> = 1; start high.
Divider 3.1 start high/low.
<0> = 0; start low.
<0> = 1; start high.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Number of clock cycles of divider 4.1 input during which 4.1 output stays low.
Number of clock cycles of 4.1 divider input during which 4.1 output stays high.
Refer to LVDSCMOS channel divider function description.
Refer to LVDSCMOS channel divider function description.
Number of clock cycles of 4.2 divider input during which 4.2 output stays low.
Number of clock cycles of 4.2 divider input during which 4.2 output stays high.
Rev. 0 | Page 76 of 84