USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 26

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USB97C100

Manufacturer Part Number
USB97C100
Description
USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
Manufacturer
Standard Microsystems Corporation
Datasheet
Notes:
Note: Interrupt events enabled by these bits are be routed to the PWR_MNG Bit 0 in the ISR_1 register.
SMSC DS – USB97C100
Any transition from high to low, or low to high on the associated input sets these bits. These bits are cleared
each time this register is read.
Since this register will report any status change, when devices are to be powered down while monitored, the
appropriate bits must be masked until the device is armed correctly.
[7:4]
BIT
[7 :4]
3
2
1
0
BIT
(0x7F2C - RESET=0x00)
3
2
1
0
(0x7F2D - RESET=0x0F)
WU_SRC_2
WU_MSK_2
NAME
IRQ3
IRQ2
IRQ1
IRQ0
NAME
IRQ3
IRQ2
IRQ1
IRQ0
'0'
'0'
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Table 31 - Wakeup Source 2 Register
Table 32 - Wakeup Mask 2 Register
Reserved
External Interrupt state since WU_SRC_2 was last read.
0 = Unchanged
1 = Changed
External Interrupt state since WU_SRC_2 was last read.
0 = Unchanged
1 = Changed
External Interrupt state since WU_SRC_2 was last read.
0 = Unchanged
1 = Changed
External Interrupt state since WU_SRC_2 was last read.
0 = Unchanged
1 = Changed
Reserved
External wakeup event enable.
0 = Enabled
1 = Masked
External wakeup event enable.
0 = Enabled
1 = Masked
External wakeup event enable.
0 = Enabled
1 = Masked
External wakeup event enable.
0 = Enabled
1 = Masked
Page 26
WAKEUP SOURCE 2
WAKEUP MASK 2
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001

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