USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 6

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

SMSC DS – USB97C100
75, 74, 68,
65, 64, 69,
70, 63, 73,
43, 72, 71,
53, 67, 80,
NUMBER
8, 20, 32,
QFP PIN
25,57,76
101,121
97, 116
77, 79
62-58,
21-24
45-52
56-54
41-34
102
30
31
99
33
42
66
44
98
78
nMASTER
IRQ[3:0]
XTAL1/
Clock In
XTAL2
EXTCLK
CLKOUT
USBD-
USDB+
FD[7:0]
FA[19:0]
nFRD
nFWR
nFCE
FALE
VCC
VCC3.3
GND
GPIO[7:0]
SYMBOL
This signal forces the USB97C100 to immediately tri-state its
external bus, even if internal transactions are not complete. All
shared ISA signals are tri-stated, except 8237 nDACKs, which
can be used in gang mode to provide external bus-master
handshaking. This pin must be used with some handshake
mechanism to avoid data corruption.
Interrupt Request 3-0; active high
These signals are driven by ISA devices on the ISA bus to
interrupt the 8051.
24MHz Crystal or clock input.
This pin can be connected to one terminal of the crystal or can
be connected to an external clock when a crystal is not used.
24MHz Crystal
This is the other terminal of the crystal.
An external clock can be used for the internal 8237. This clock
can be used to synchronize the 8237 to other devices.
This clock frequency is the same as the 8051 running clock.
This clock is stopped when the 8051 is stopped. Peripherals
should not use this clock when they are expected to run when
the 8051 is stopped. This clock can be used to synchronize
other devices to the 8051.
USB Upstream Connection signals
These are two point-to-point signals and driven differentially.
These signals are used to transfer data between 8051 and the
external FLASH.
These signals address memory locations within the FLASH.
Flash ROM Read; active low
Flash ROM Write; active low
Flash ROM Chip Select; active low
+3.3V power or 5V
+3.3V power for USB
Ground Reference
General Purpose I/O.
These pins can be configured as inputs or outputs under
software control.
External Bus master, active low
Alternate clock to 8237
Clock output.
Flash ROM Address Bus
Flash ROM address latch enable
FLASH INTERFACE
MISCELLANEOUS
POWER SIGNALS
USB INTERFACE
Page 6
Flash ROM Data Bus
PIN DESCRIPTION
BUFFER
OCLKx
TYPE
ICLKx
I/O16
ICLK
IO-U
Rev. 01/03/2001
IO8
O8
O8
O8
O8
O8
O8
IP
I