AD9927 Analog Devices, AD9927 Datasheet - Page 18

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

AD9927
Digital Data Outputs
The AD9927 data output and DCLK phase are programmable
using the DOUTPHASE registers (Address 0x38, Bits [11:0]).
DOUTPHASEP (Bits [5:0]) selects any edge location from 0 to
63, as shown in Figure 21. DOUTPHASEN (Bits [11:6]) does
not actually program the phase of the data outputs but is used
internally and should always be programmed to a value of
DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP
is set to 0, DOUTPHASEN should be set to 32 (0x20).
H1, H3, H5, H7
H2, H4, H6, H8
POSITION
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
2. CONNECT H1, H3, H5, AND H7 TOGETHER AND H2, H4, H6, AND H8 TOGETHER FOR MAXIMUM DRIVE STRENGTH.
PERIOD
SIGNAL
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
PIXEL
CCD
RG
HL
RGr[0]
HLr[0]
H1r[0]
P[0]
H1, H3
H2, H4
H5, H7
H6, H8
1
H1 TO H8 PROGRAMMABLE EDGES:
1
2
3
4
3
H1 RISING EDGE.
H1 FALLING EDGE.
H5 RISING EDGE.
H5 FALLING EDGE.
Figure 20. High Speed Timing Default Locations
RGf[16]
P[16]
2
Figure 19. HCLK Mode 3 Operation
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SHP[32]
HLf[32]
H1f[32]
P[32]
Normally, the DOUT and DCLK signals track in phase, based
on the contents of the DOUTPHASE registers. The DCLK output
phase can also be held fixed with respect to the data outputs by
changing the DCLKMODE register high (Address 0x38, Bit [12]).
In this mode, the DCLK output remains at a fixed phase equal
to a delayed version of CLI while the data output phase is still
programmable.
The pipeline delay through the AD9927 is shown in Figure 22.
After the CCD input is sampled by SHD, there is a 16-cycle
delay until the data is available.
P[48]
t
S1
P[64] = P[0]
SHD[0]