AD9927 Analog Devices, AD9927 Datasheet - Page 92

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

AD9927
Address
A6
A7
A8
A9
AA
Table 57. Update Control Registers
Address
B0
B1
B2
B3
B4
B5
Table 58. Extra Registers
Address
D4
D7
D8
Data
Bits
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Data
Bits
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[0]
[1]
[2]
[3]
[0]
[1]
[9:2]
[0]
[1]
[27:0]
Data Bits
FFF9
Default Value
1803
E7FC
F8FD
0702
0006
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
Default Value
0
0
0
0
0
0
Update
Type
VD
VD
VD
VD
VD
VD
VD/SG
VD/SG
Update
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
Update
Name
GP8_TOG2_LN
GP8_TOG2_PX
GP8_TOG3_FD
GP8_TOG3_LN
GP8_TOG3_PX
GP8_TOG4_FD
GP8_TOG4_LN
GP8_TOG4_PX
SUBCK_TOG1_13
SUBCK_TOG2_13
SUBCKHP_TOG1_13
SUBCKHP_TOG2_13
Name
AFE_UPDT_SCK
AFE_UPDT_VD
MISC_UPDT_SCK
MISC_UPDT_VD
VDHD_UPDT_SCK
VDHD_UPDT_VD
START
Name
TEST
GPO_INT_EN
TEST
TEST
XV24_SWAP
Rev. 0 | Page 92 of 100
Description
Each bit corresponds to one address location.
AFE_UPDT_SCK [0] = 1, update Address 0x00 on SL rising edge.
AFE_UPDT_SCK [1] = 1, update Address 0x01 on SL rising edge.
…
AFE_UPDT_SCK [15] = 1, update Address 0x0F on SL rising edge.
Each bit corresponds to one address location.
AFE_UPDT_VD [0] = 1, update Address 0x00 on VD rising edge.
AFE_UPDT_VD [1] = 1, update Address 0x01 on VD rising edge.
…
AFE_UPDT_VD [15] = 1, update Address 0x0F on VD rising edge.
Enable SCK update of miscellaneous registers,
Address 0x10 to Address 0x1F.
Enable VD update of miscellaneous registers,
Address 0x10 to Address 0x1F.
Enable SCK update of VDHD registers, Address 0x20 to Address 0x2F.
Enable VD update of VDHD registers, Address 0x20 to Address 0x2F.
Description
General-Purpose Signal 8, second toggle position, line location.
General-Purpose Signal 8, second toggle position, pixel location.
General-Purpose Signal 8, third toggle position, field location.
General-Purpose Signal 8, third toggle position, line location.
General-Purpose Signal 8, third toggle position, pixel location.
General-Purpose Signal 8, fourth toggle position, field location.
General-Purpose Signal 8, fourth toggle position, line location.
General-Purpose Signal 8, fourth toggle position, pixel location.
Bit [13] for SUBCK Toggle Position 1. For 14-bit H-counter mode.
Bit [13] for SUBCK Toggle Position 2. For 14-bit H-counter mode.
Bit [13] for SUBCK HP Toggle 1. For 14-bit H-counter mode.
Bit [13] for SUBCK HP Toggle 2. For 14-bit H-counter mode.
Test use only. Set to 0.
Allow observation of internal signals at GPO5 to GPO8 outputs.
Test use only. Set to 0.
Test use only. Set to 0.
Recommended start-up register. Should be set to 0x888.
Description
GPO5: OUTCONTROL.
GPO6: HBLK.
GPO7: CLPOB.
GPO8: PBLK.
Set to 1 to change the V-driver output configuration so that XV15 is
output on the XV24 output pin. Useful with special vertical
sequence alternation mode when the XV24 register is reserved for
pattern selection.