AD9927 Analog Devices, AD9927 Datasheet - Page 88

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

AD9927
Address
33
34
35
36
37
38
39
Table 54. Test Registers—Do Not Access
Address
3E ~ 4F
Table 55. Test Registers—Do Not Access
Address
50 ~ 6F
Table 56. Shutter and GPO Registers
Address
70
Data
Bits
[5:0]
[13:8]
[16]
[0]
[1]
[2]
[3]
[7:4]
[2:0]
[6:4]
[10:8]
[14:12]
[18:16]
[22:20]
[2:0]
[6:4]
[10:8]
[14:12]
[5:0]
[11:6]
[17:12]
[5:0]
[11:6]
[12]
[14:13]
[15]
[2:0]
Data
Bits
[2:0]
[5:3]
Data Bits
Data Bits
0
20
Default
Value
0
10
1
0
0
0
0
4
1
1
1
1
1
1
1
1
1
1
10
0
20
0
0
0
7
Default
Value
0
0
Update
Type
SCK
SCK
SCK
SCK
SCK
SCK
SCK
Update
Type
VD
Default Value
Default Value
RGNEGLOC
RGH2POL
HCLK_WIDTH
H3DRV
H7DRV
SHDLOC
SHPLOC
DOUTPHASEP
DCLKMODE
Name
RGPOSLOC
H1HBLKRETIME
H2HBLKRETIME
HLHBLKRETIME
HL_HBLK_EN
H1DRV
H2DRV
H4DRV
HLDRV
RGDRV
H5DRV
H6DRV
H8DRV
SHPWIDTH
DOUTPHASEN
DOUTDELAY
DCLKINV
CPHMASK
Name
PRIMARY_ACTION
SECOND_ACTION
Update Type
Update
Rev. 0 | Page 88 of 100
Description
RG rising edge location.
RG falling edge location.
RG polarity control. 0: inverse of Figure 20, 1: no inversion.
Retime H1, H2, HL HBLK to the internal clock. 0: no retime; 1: retime.
Recommended setting is retime enabled (1). Setting to 1 adds one cycle delay
to programmed HBLK positions.
Enable HBLK for HL output. 0: disable; 1: enable.
Enables wide H-clocks during HBLK interval. Set to 0 to disable.
H1 drive strength. 0: off; 1: 4.3 mA; 2: 8.6 mA; 3: 12.9 mA; 4: 4.3 mA;
5: 8.6 mA; 6: 12.9 mA; 7: 17.2 mA.
H2 drive strength (same range as H1DRV).
H3 drive strength (same range as H1DRV).
H4 drive strength (same range as H1DRV).
HL drive strength (same range as H1DRV).
RG drive strength (same range as H1DRV).
H5 drive strength (same range as H1DRV).
H6 drive strength (same range as H1DRV).
H7 drive strength (same range as H1DRV).
H8 drive strength (same range as H1DRV).
SHD sampling edge location.
SHP sampling edge location.
SHP width (controls input dc restore switch active time).
DOUT phase control, positive edge. Specifies location of DOUT.
DOUT phase control, negative edge. Always set to DOUTPHASEP plus
32 edges to maintain 50% duty cycle of internal DOUTPHASE clocking.
DCLK mode. 0: DCLK tracks DOUT; 1: DCLK phase is fixed.
Data output delay (t
0: no delay; 1: ~3 ns; 2: ~6 ns; 3: ~9 ns
Invert DCLK output. 0: no inversion, 1: inversion of DCLK.
Enable H-masking during CP operation.
Description
Selects action for primary and secondary counters.
0: idle (do nothing) autoreset on VD.
1: activate counter (primary: auto exposure/readout).
2: RapidShot: wrap/repeat counter.
3: ShotTimer: delay start of count.
4: ShotTimer with RapidShot.
5: SLR exposure (manual).
Name
OD
) with respect to DCLK rising edge.
Name
Description
Test registers only. Do not access.
Test registers only. Do not access.
Description