CY3130R62 Cypress Semiconductor Corp., CY3130R62 Datasheet - Page 5

• Manufacturer Part Number: CY3130R62
• Description: Warp Enterprise VHDL PC
• Manufacturer: Cypress Semiconductor Corp.

the logical flow the designer takes through a project and re-
members what steps have been completed on which designs.
Source-Level Simulation
Warp Enterprise’s source-level behavioral simulator helps you
catch problems with your code early in the design process by
letting you simulate a design before synthesis. The tool lets
you graphically watch inputs and outputs, gives you timing in-
formation and allows you to step through your code line by line.
Compilation
Once the VHDL description of the design is complete, it is
compiled using Warp Enterprise. Although implementation is with
a single command, compilation is actually a multistep process, as
shown in Figure 1.
The first part of the compilation process is the same for all
devices. The input description is synthesized to a logical rep-
resentation of the design. Warp synthesis is unique in that the
input
descriptions. Competing programmable logic compilers re-
quire very specific and device-dependent information in the
design description. Warp synthesis is based on UltraGen tech-
nology that allows Warp Enterprise to infer adders, subtrac-
tors, multipliers, comparators, counters and shifters from the
behavioral descriptions. Warp Enterprise then replaces these
operators internally with an architecture-specific circuit. This
circuit or “module” is also pre-optimized for either area or
speed. Warp Enterprise uses the appropriate implementation
based on user directives.
The second step of compilation is an iterative process of opti-
mizing the design and fitting the logic into the targeted device.
Logical optimization in Warp Enterprise is accomplished using
Espresso algorithms. The optimized design is automatically fed to
the Warp Enterprise fitter for targeting a PLD or CPLD. This fitter
supports the automatic or manual placement of pin assignments as
well as automatic selection of D or T flip-flops. After optimization and
fitting, Warp Enterprise creates a JEDEC or Intel hex file for the
specified PLD or CPLD.
Automatic Error Tracking
Warp Enterprise features automatic error location that allows
problems to be diagnosed and corrected in seconds. Errors
from compilation are displayed immediately in a window. If the
user highlights a particular error, Warp Enterprise will automat-
ically open the source code file and highlight the offending line
in the entered design. If the device fitting process includes
errors, a window will again describe them. A detailed report file
is generated indicating the resources required to fit the input
design and any problems that occurred in the process.
Timing Simulation
The Aldec Active-HDL Sim post-fitting timing simulator pro-
vides timing simulation for PLDs/CPLDs and features interac-
tive waveform viewing as well as graphical creation and editing
of all waveforms. The simulator also provides the ability to
probe internal nodes, and automatically generate clocks and
pulses. The version in Warp Enterprise has the ability to com-
pare waveforms and highlight differences before and after a
Document #: 38-03050 Rev. *A
languages
support
device-independent
design
design change. Warp Enterprise has unlimited simulation
time. To use the timing simulator in Warp Enterprise VHDL you
must use a VHDL netlist.
Warp Enterprise VHDL will also output standard VHDL timing
models. These models can be used with all third-party
simulators to perform functional and timing verifications of the
synthesized design.
Architecture Explorer
The Architecture Explorer graphically displays how the design
will be implemented on the chip. It provides a view of the entire
device to show what memory elements and logic clusters have
been used for what part of the design. This gives the designer
an idea of what resources are free. The Architecture Explorer
allows you to zoom in multiple times. At maximum zoom it
displays the logic gate implementation in each macrocell. The
Architecture Explorer is available for PSI, Delta39K, and
Quantum38K devices.
Timing Analyzer
The Timing Analyzer gives the time across any path as well as
the breakdown of what steps are causing the timing delays.
This tool does not simply display the general specification for
the target device but a worst-case simulation of the actual path
being taken through the device. When you highlight a path on
the timing analyzer, the source and destination of that path are
displayed on the Architecture Explorer. The timing analyzer
graphical interface is available for PSI, Delta39K, and
Quantum38K devices.
Programming
Cypress’s F
In-System Reprogrammable™ (ISR™) devices can be pro-
grammed on board with an ISR programmer. For PSI,
Delta39K, and Quantum38K devices, Warp Enterprise pro-
duces an Intel hex file. The ISR programmer converts this file
into STAPL and programs the device. For Ultra37000 and
F
For Ultra37000, the ISR programmer converts this file into
JAM/STAPL and programs the device. For F
DEC file is used directly to program the device.
Warp Enterprise comes with an UltraISR Programming Cable
and a Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin device.
The JEDEC and Intel hex files produced by Warp Enterprise
can also be used with any qualified third party programmer to
program Cypress CPLDs.
For more information on Cypress’s ISR software see the ISR
Programming Kit (CY3900i) data sheet.
Warp Software System Requirements
• IBM PC or equivalent (Pentium
• 32 MB of RAM (64 Mbytes recommended)
• 110 MB Disk Space
• CD-ROM drive
• Windows 98, or Windows NT 4.0
• Warp Enterprise for VHDL Hardware Key
LASH
370i devices, Warp Enterprise produces a JEDEC file.
LASH
370i, Ultra37000, Quantum38K and Delta39K
®
class recommended)
LASH
CY3130
370i, the JE-
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