MAX104 Maxim, MAX104 Datasheet - Page 23

• Manufacturer Part Number: MAX104
• Description: 5V / 1Gsps / 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
• Manufacturer: Maxim

asserted, the auxiliary port contained “even” samples
while the primary port contained “odd” samples. After
the RSTOUT is deasserted (which marks the start of the
DREADY clock’s reset phase), note that the order of the
samples in the ports has been reversed. The auxiliary
port also contains an out-of-sequence sample. This is a
consequence of the “swallowed” clock cycle that was
needed to resynchronize DREADY to the reset phase.
Also note that the older sample data is always in the aux-
iliary port, regardless of the DREADY phase.
These examples illustrate the combinations that result
with a reset input signal of two clock cycles. It is also
possible to reset the internal MAX104 demux success-
fully with a reset pulse of only one clock cycle, provided
that the setup-time and hold-time requirements are met
with respect to the sample clock. However, this is not
recommended when additional external demuxes are
used.
Note that many external demuxes require that their
reset signals be asserted while they are clocked, and
may require more than one clock cycle of reset. More
importantly, if the phase of the DREADY clock is such
that a clock pulse will be “swallowed” to resynchronize,
Figure 19. Reset Output Timing in Demuxed DIV2 Mode (DREADY Realigned)
DATA PORT
DATA PORT
DATA PORT
RESET OUT
NOTE: DREADY PHASE WAS ADJUSTED TO MATCH THE RESET PHASE BY “SWALLOWING” ONE INPUT CLOCK CYCLE.
AUXILIARY
PRIMARY
DREADY
RESET
INPUT
CLK
THE AUXILIARY PORT CONTAINS AN OUT-OF-SEQUENCE SAMPLE AS A RESULT OF THE DELAY.
CLK+
CLK-
n
RSTIN+
RSTIN-
______________________________________________________________________________________
DREADY+
DREADY-
ADC SAMPLE NUMBER
n+1
t
SU
On-Chip 2.2GHz Track/Hold Amplifier
n+2
RSTOUT+
RSTOUT-
n+3
t
HD
n+4
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+5
±5V, 1Gsps, 8-Bit ADC with
n+6
then no reset output will occur at all. In effect, the
RSTOUT signal will be “swallowed” with the clock
pulse. The best method to ensure complete system
reset is to assert RSTIN for the appropriate number of
DREADY clock cycles required to complete reset of the
external demuxes.
For applications that require monitoring of the die tem-
perature, it is possible to determine the die temperature
of the MAX104 under normal operating conditions by
observing the currents I
ICONST and IPTAT. I
(nominal) currents that are designed to be equal at
+27°C. These currents are derived from the MAX104’s
internal precision +2.5V bandgap reference. I
designed to be temperature independent, while I
directly proportional to the absolute temperature. These
currents are derived from pnp current sources refer-
enced from V
nected to GNDI. The contacts ICONST and IPTAT may
be left open, because internal catch diodes prevent
saturation of the current sources. The simplest method
n+7
n-2
n-1
n+8
CC
n+9
Die Temperature Measurement
I and driven into two series diodes con-
OUT-OF-SEQUENCE SAMPLE
n+10
n+1
CONST
n
CONST
n+11
and I
CLOCK PULSE “SWALLOWED”
and I
PTAT
n+12
PTAT
n+2
n+4
are two 100µA
n+13
, at contacts
CONST
PTAT
23
is
is