T8536B ETC-unknow, T8536B Datasheet - Page 24

• Manufacturer Part Number: T8536B
• Description: T8535b/t8536b Quad Programmable Codec
• Manufacturer: ETC-unknow

T8535B/T8536B Quad Programmable Codec
Functional Description
Reset Functionality
A 0.1 F capacitor between the RST lead and ground
will effectively hold the lead low long enough to reset
the device on powerup, allowing for a cost-effective
power-on reset function. Notice that the memory must
be reloaded through the serial interface after a hard-
ware reset function. For proper operation, it is neces-
sary for FS and BCLK to be present and stable during
a reset. A wait period for the internal PLL to stabilize is
required after reset goes high. See the timing diagram
shown in Figure 20 for the proper hardware or power-
on reset procedure.
For a software reset, the control memory should not be
accessed for a minimum of 256 s following the reset.
Memory Control Mapping
Several memory locations are used to control the
device. The software interface tables (Table 20, Mem-
ory Mapping, and Table 21, Control Bit Definition) show
the memory assignments that are useful in call pro-
cessing and system testing. It should be noted that
other memory locations are used by the device to hold
intermediate results and other device state information.
Writing to these other locations can cause serious dis-
ruptions in the operation of the device and should be
avoided.
Standby Mode
The device enters a low-power standby mode with
powerup or software reset, or by programming the
CHACTIVE register 129, bit 0. In standby mode, the
control interface is active, capable of writing or reading
registers. SLIC read and write data latches are also
active. Analog signals at VF
are ignored in this mode. BCLK must be present for
proper standby mode operation.
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24
(continued)
X
I and PCM signals at D
(continued)
R
Test Capabilities
The device has several built-in test capabilities that can
be used to verify correct operation of the signal pro-
cessing of the line card. These test functions are
accessed in several different control addresses. Five
loopback modes are employed: the first for the digital
signal from the PCM bus to be looped back to the PCM
bus. This loopback facility can be used to verify correct
operation of the PCM bus interface logic, as well as
operation of the PCM bus. The second digital loopback
function allows complete testing of the digital process-
ing capability of the codec by looping the data back at
the analog/digital conversion interface. The third loop-
back function can be used to check the operation of all
the signal processing performed in the device, includ-
ing the conversions to/from analog. These digital loop-
back functions can be used with tone generation and
reception via the PCM bus.
The first analog loopback facility is at the digital side of
the delta-sigma converters and loops analog transmit
data back to the analog receive path. The second ana-
log loopback is at the PCM bus interface and loops the
transmit data from the line back to the receive path.
By assigning the transmit and receive time slots identi-
cally, a loopback arrangement at the PCM bus can be
effectively programmed for signals generated on the
line side of the codec. This mode is useful for testing
from the line side through the entire device.
SLIC Control Capabilities
Memory locations 158, 159, and 160 are used to con-
trol six bidirectional latches that are intended to allow
the serial interface to control other line card devices,
such as ringing/test switches, telecom electromechani-
cal relays, and SLIC devices. When the TTL latches
are configured as outputs, external devices should be
set up to sink current from the latch. Location 158 sets
the operational mode of these latches as either inputs
or outputs. Location 159 specifies what is to be written
on the latch leads driven by the device. Location 160
reports the actual state of these leads. It should be
noted that a channel control reset forces all of these
external leads, except those corresponding to bits 2
and 3, to the high-impedance state, so any inputs con-
nected to bits 0, 1, 4, and 5 should have appropriate
pull-up or pull-down resistors (off-chip, if required) to
force the external device into a known state at power-
up or in the event of a reset. Bits 2 and 3 will reset to
outputs with a value of zero.
September 2001
Agere Systems Inc.