HFC-S Cologne Chip AG, HFC-S Datasheet - Page 11

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

HFC-S
2.11
RESET characteristics
The reset signal (hardware reset and soft reset) must be active for at least 4 clock cycles.
The PCM30 bus lines STIO1 and STIO2 and the interrupt lines are in tristate mode after a reset.
The HFC-S is in slave mode after reset.
C4IO and F0IO are inputs.
The lines F1_A and F1_B are '0'.
In the processor modes DMARQ1 and DMARQ2 are inactive ('0').
The S/T state machine is stuck to '0' after reset. This means the HFC-S does not react to any signal on
the S/T interface before the S/T state machine is initialised.
Registers which are cleared are explained in the register section of this data sheet.
March 1997
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