HFC-S Cologne Chip AG, HFC-S Datasheet - Page 24

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

HFC-S
3.5.1.5 FIFO initialisation
All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET. The RESET signal
must have a length of at least 4 clock cycles.
Then the result is Z1 = Z2 = 1FFF
and F1 = F2 = 1F
for the B-channels
h
h
and Z1 = Z2 = 1FFh and F1 = F2 = 1Fh for the D-channel.
Please mask bit 4 of D-channel from counter F1, F2.
The same initialisation is done if the bit 3 in the CIRM register is set (soft reset).
3.5.2 Transparent mode of HFC-S
You can switch off HDLC operation for each B-channel independently. There is one bit for each B-
channel in the CTMT control register. If this bit is set data in the FIFO is send directly to the S/T or
PCM30 bus interface and data from the S/T or PCM30 bus interface is send directly to the FIFO.
Be sure to switch into transparent mode only if F1=F2. Being in transparent mode the Fx counters
remain unchanged. Z1 and Z2 are the input and output pointers respectively. Because F1=F2 both Z-
counters are always accessable and have valid data.
If a send FIFO channel changes to FIFO empty condition no CRC is generated and the last data byte
written into the FIFO is repeated until there is new data.
In receive channels there is no check on flags or correct CRCs and no status byte is added.
The byte bounderies are not arbitrary like in HDLC mode where byte synchronisation is achieved
with HDLC-flags. The data is just the same as it comes from the S/T or PCM30 bus interface or is
send to this.
Because Fx incrementation dummy registers are not used you can send and receive transparent data
in two shapes. The normal and first shape is tranporting B-channel data with the LSB first as it is
usual in HDLC mode. The second shape is sending the bytes upside down as it is normal for PWM
data. So the first bit is the MSB.
March 1997
24 of 57