HFC-S Cologne Chip AG, HFC-S Datasheet - Page 34

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

4.4
March 1997
Name
CIRM
CTMT
Register bit description of interrupt, status and control registers
(18h)
(19h)
Bits
2..0
3
4
7..5
0
1
2
4, 3
5
r/w
w
w
w
w
w
w
w
Function
select IRQ channel in PC mode
'000' IRQ disable (reset default)
'001' IRQ_A
'010' IRQ_B
'011' IRQ_C
'100' IRQ_D
'101' IRQ_E
'110' IRQ_F
'111' IRQ disable
soft reset, similar as hardware reset; the registers CIP,
CIRM and CTMT are not changed so selected I/O address
is kept in ISA-PC mode. The reset is active until the bit is
cleared.
'1'
'0'
select memory
'0'
'1'
ignored
HDLC/transparent mode for channel B1
'0'
'1'
HDLC/transparent mode for channel B2
'0'
'1'
ignored
select timer and watchdog
'00'
'01'
'10'
'11'
timer/watchdog reset mode
'0'
'1'
activate reset
deactivate reset (reset default)
32k x 8 external RAM (reset default)
HDLC mode (reset default)
transparent mode
HDLC mode (reset default)
transparent mode
timer
25ms
50ms
400ms
800ms
reset timer/WD by CTMT bit 7 (reset default)
automatically reset timer/WD at each access to
HFC-S
8k x 8 external RAM
watchdog
50ms
100ms
800ms
1600ms
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HFC-S