WM8581 Wolfson Microelectronics Ltd., WM8581 Datasheet - Page 31

• Manufacturer Part Number: WM8581
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
AUDIO INTERFACE CONTROL
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The register bits controlling the audio interfaces are summarized below. Dynamically changing the
audio data format may cause erroneous operation, and is not recommended.
Interface timing is such that the input data and LRCLK are sampled on the rising edge of the interface
BCLK. Output data changes on the falling edge of the interface BCLK. By setting the appropriate bit
clock polarity control register bits, e.g. PAIFRXBCP, the polarity of BCLK may be reversed, allowing
input data and LRCLK to be sampled on the falling edge of BCLK. Setting the bit clock polarity
register for a transmit interface results in output data changing on the rising edge of BCLK.
Similarly, the polarity of left/right clocks can be reversed by setting the appropriate left right polarity
bits, e.g. PAIFRXLRP.
REGISTER
ADDRESS
PAIF 3
PAIF 4
R12
0Ch
R13
0Dh
BIT
1:0
3:2
1:0
3:2
4
5
4
PAIFRXFMT
PAIFRXBCP
PAIFRXLRP
PAIFTXFMT
PAIFTXLRP
PAIFRXWL
PAIFTXWL
LABEL
[1:0]
[1:0]
[1:0]
[1:0]
DEFAULT
10
10
10
10
0
0
0
PAIF Receiver Audio Data Format
Select
PAIF Receiver Audio Data Word
Length
In LJ/RJ/I
In DSP Format:
PAIF Receiver BCLK polarity
PAIF Transmitter Audio Data Format
Select
PAIF Transmitter Audio Data Word
Length
In LJ/RJ/I
In DSP Format:
11: DSP Format
10: I
01: Left justified
00: Right justified
11: 32 bits (see Note 1,2)
10: 24 bits
01: 20 bits
00: 16 bits
0 = LRCLK not inverted
1 = LRCLK inverted
0 = DSP Mode A
1 = DSP Mode B
0 = BCLK not inverted
1 = BCLK inverted
11: DSP Format
10: I
01: Left justified
00: Right justified
11: 32 bits (see Note 1,2)
10: 24 bits
01: 20 bits
00: 16 bits
0 = LRCLK not inverted
1 = LRCLK inverted
0 = DSP Mode A
1 = DSP Mode B
2
2
2
2
S Format
S Format
S modes
S modes
DESCRIPTION
PD Rev 4.0 April 2007
WM8581
31