WM8581 Wolfson Microelectronics Ltd., WM8581 Datasheet - Page 52

• Manufacturer Part Number: WM8581
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8581
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Table 42 PLL Control Register Function in PLL User and PLL S/PDIF Receiver Modes
PLL CONFIGURATION
The PLLs perform a configurable frequency multiplication of the input clock signal (f
multiplication factor of the PLL (denoted by ‘R’) is variable and is defined by the relationship: R = (f
f
The multiplication factor for each PLL is set using register bits PLLx_N and PLLx_K (refer to Table 41). The
multiplication effect of both the N and K multipliers are additive (i.e. if N is configured to provide a
multiplication factor of 8 and K is configured to provide a multiplication factor of 0.192, the overall
multiplication factor is 8 + 0.192 = 8.192).
In order to choose and configure the correct values for PLLx_N and PLLx_K, multiplication factor R
must first be calculated. Once value R is calculated, the value of PLLx_N is the integer (whole
number) value of R, ignoring all digits to the right of the decimal point. For example, if R is calculated
to be 8.196523, PLL_N is simply 8.
Once PLLx_N is calculated, the PLLx_K value is simply the integer value of (2
example, if R is 8.196523 and PLLx_N is 8, PLLx_K is therefore (2
(ignoring all digits to the right of the decimal point).
Note: the PLLs are designed to operate with best performance (shortest lock time and optimum
stability) when f
lie in the range 5 ≤ PLLx_N ≤ 13.
Each PLL has an output divider to allow the f
use as the source for the MCLK and CLKOUT outputs, the S/PDIF transmitter and the internal ADC
and DACs. The divider output is configurable and is set by the FREQMODE_A or FREQMODE_B
bits in conjunction with the POSTSCALE_A and POSTSCALE_B bits. Each PLL is also equipped
with a pre-scale divider which offers frequency divide by one or two before the OSCCLK signal is
input into the PLL. Please refer to Table 43 for details.
Table 41 User Mode PLL_K and PLL_N Multiplier Control
1
).
REGISTER
ADDRESS
06h
POSTSCALE_A
POSTSCALE_B
FREQMODE_A
FREQMODE_B
PRESCALE_A
PRESCALE_B
Parameter
PLLA_N
PLLA_K
PLLB_N
PLLB_K
2
is between 90 and 100MHz and PLLx_N is 8. However, acceptable PLLx_N values
BIT
7:4
PLL_N[3:0]
PLL User Mode
LABEL
Manual
Manual
Manual
Manual
Manual
Manual
Manual
Manual
Manual
Manual
2
clock signal to be divided to a frequency suitable for
DEFAULT
0111
Configure Specified PLLB Frequency
Configure Specified PLLB Frequency
Configure Specified PLLB Frequency
256fs/128fs PLLACLK Select
PLL S/PDIF Receiver Mode
Write PRESCALE_B Value
Automatically Controlled
Automatically Controlled
Automatically Controlled
Integer (N) part of PLLB frequency
ratio (R).
Use values in the range 5 ≤ PLLB_N
≤ 13 as close as possible to 8
Note: PLLB_N must be set to
specific values when the S/PDIF
receiver is used. Refer to S/PDIF
Receive Mode Clocking section
for details.
Not Used
Not Used
22
(8.196523-8)), which is 824277
DESCRIPTION
PD Rev 4.0 April 2007
22
(R-PLLx_N)). For
Production Data
1
). The
2
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