WM8581 Wolfson Microelectronics Ltd., WM8581 Datasheet - Page 79

• Manufacturer Part Number: WM8581
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
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REGISTER
ADDRESS
DEVREV
PLLA 1/
DEVID1
PLLA 2/
DEVID2
PLLA 3/
PLLA 4
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
00h
01h
02h
03h
R0
R1
R2
R3
SPDRXCHAN 1
SPDRXCHAN 2
SPDRXCHAN 3
SPDRXCHAN 4
SPDRXCHAN 5
READBACK
SPDMODE
PWRDN 1
PWRDN 2
SPDSTAT
INTMASK
Reserved
INTSTAT
RESET
GPO1
GPO2
GPO3
GPO4
BIT
8:0
8:0
3:0
7:4
0
1
POSTSCALE_A
PLLA_K[21:18]
PRESCALE_A
PLLA_K[17:9]
PLLA_N[3:0]
PLLA_K[8:0]
LABEL
2A
2B
2C
2D
2E
24
25
26
27
28
29
2F
30
31
32
33
34
35
ALWAYSVALID
FILLMODE
0
0
0
0
0
0
0
100100001
101111110
DEFAULT
1101
0111
0
0
0
0
0
0
1
0
ALLDACPD
WL_MASK
GPO2OP[3:0]
GPO4OP[3:0]
GPO6OP[3:0]
1
0
0
0
Fractional (K) part of PLLA frequency ratio (R).
Value K is one 22-digit binary number spread over registers R0,
R1 and R2 as shown.
Reading from these registers will return the device ID.
Device ID readback is not possible in continuous readback mode
(CONTREAD=1).
Integer (N) part of PLLA frequency ratio (R).
Use values in the range 5 ≤ PLLA_N ≤ 13 as close as possible to
8.
Reading from this register will return the device revision number.
PLL Pre-scale Divider Select
0 = Divide by 1 (PLL input clock = oscillator clock)
1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2)
PLL Post-scale Divider Select
PLL S/PDIF Receiver Mode
POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK,
POSTSCALE_B is not used. Refer to Table 45.
PLL User Mode
Used in conjunction with the FREQMODE_x bits. Refer to Table
44.
Error Flag Interupt Status Register
Note: PRESCALE_A must be set to the same value as
PRESCALE_B in PLL S/PDIF receiver mode.
SPDIFRXD
Channel Status Register 1
Channel Status Register 2
Channel Status Register 3
Channel Status Register 4
Channel Status Register 5
1
0
S/PDIF Status Register
1
0
R0 returns 10000001 = 81h
R1 returns 10000101 = 85h
MASK[8:0]
RESET
SPDIFTXD
READEN
1
1
DACPD[3:0]
1
SPDIFPD
CONTREAD
1
1
DESCRIPTION
PLLBPD
GPO1OP[3:0]
GPO5OP[3:0]
RXINSEL[1:0]
GPO30P[3:0]
GPO70P[3:0]
0
READMUX[2:0]
PLLAPD
ADCPD
0
PD Rev 4.0 April 2007
SPDIFIN1MODE
OSCPD
PWDN
0
WM8581
000111001
000000000
000010000
000110010
001010100
001110110
010011000
001111110
000111110
000000000
n/a
-
-
-
-
-
-
-
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