WM8978 Wolfson Microelectronics Ltd., WM8978 Datasheet - Page 72
Manufacturer Part Number
The WM8978 is a low power, high quality stereo codec designed for portable applications such as Digital still camera or Digital Camcorde
Wolfson Microelectronics Ltd.
AUDIO SAMPLE RATES
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
Table 53 Sample Rate Control
The PLL can be enabled or disabled by the PLLEN register bit.
Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are
set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
Table 54 PLLEN Control Bit
The WM8978 sample rates for the ADCs and the DACs are set using the SR register bits. The
cutoffs for the digital filters and the ALC attack/decay times stated are determined using these
values and assume a 256fs master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the
closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack,
decay and hold times will scale appropriately.
The WM8978 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8978 audio functions from another external clock, e.g. in
Generate and output (on pin CSB/GPIO1 and/or GPI04) a clock for another part of the system that is
derived from an existing audio master clock.
Figure 40 shows the PLL and internal clocking arrangment on the WM8978.
Approximate sample rate (configures the
coefficients for the internal digital filters):
PTD Rev 2.6 November 2005
Preliminary Technical Data