WM8978 Wolfson Microelectronics Ltd., WM8978 Datasheet - Page 73

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WM8978

Manufacturer Part Number
WM8978
Description
The WM8978 is a low power, high quality stereo codec designed for portable applications such as Digital still camera or Digital Camcorde
Manufacturer
Wolfson Microelectronics Ltd.
Datasheet

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Preliminary Technical Data
Figure 40 PLL and Clock Select Circuit
w
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a
selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
Table 55 PLL Frequency Ratio Control
The PLL performs best when f
are shown in Table 56.
The PLL frequency ratio R = f
R36
PLL N value
R37
PLL K value
1
R38
PLL K Value
2
R39
PLL K Value
3
REGISTER
ADDRESS
PLLN = int R
PLLK = int (2
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 2
4
3:0
5:0
8:0
8:0
BIT
24
x (8.192 – 8)) = 3221225 = 3126E9h
24
PLLPRESCALE
PLLN
PLLK [23:18]
PLLK [17:9]
PLLK [8:0]
(R-PLLN))
2
2
/f
1
LABEL
is around 90MHz. Its stability peaks at N=8. Some example settings
(see Figure 40) can be set using the register bits PLLK and PLLN:
2
= 4 x 2 x 12.288MHz = 98.304MHz.
0
1000
0Ch
093h
0E9h
DEFAULT
PLL
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
Divide MCLK by 2 before input to
PTD Rev 2.6 November 2005
DESCRIPTION
WM8978
73