WM8959 Wolfson Microelectronics Ltd., WM8959 Datasheet - Page 104

• Manufacturer Part Number: WM8959
• Description: Mobile Multimedia DAC with Dual-mode Class AB/D Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8959
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CLOCKING AND SAMPLE RATES
Figure 78 Clocking Scheme
MCLK
SYSCLK
All internal clocks are derived from SYSCLK.
SYSCLK can be derived directly from MCLK or from the PLL output and has a
programmable divide by 2 option (MCLKDIV).
DAC_CLKDIV
DAC sample rate is set by DAC_CLKDIV (Master or slave mode).
DACLRC_RATE
DACLRC in master mode is derived from BCLK and is controlled by DACLRC_RATE.
BCLK_DIV
BCLK rate is set by BCLK_DIV in master mode.
OPCLKDIV
GPIO Clock output frequency is set by OPCLKDIV.
DCLKDIV
Class D switching clock frequency is set by DCLKDIV and should be between 700kHz
and 800kHz for best performance.
TOCLK_RATE
A slow clock is used for button/accessory detect de-bounce and for volume update
timeouts (when zero-cross detect is enabled). The frequency of this slow clock is set by
TOCLK_RATE.
Other Sample Rate Controls
DEEMP configures the de-emphasis filter for the chosen sample rate.
MCLK_INV
f/2
The internal clocks for the DACs, DSP core functions, digital audio interface and Class D switching
amplifier are all derived from a common internal clock source, SYSCLK.
SYSCLK can either be derived directly from MCLK, or may be generated from a PLL using MCLK as
an external reference. Many commonly-used audio sample rates can be derived directly from typical
MCLK frequencies; the PLL provides additional flexibility for a wide range of MCLK frequencies. All
clock configurations must be set up before enabling playback to avoid glitches.
The DAC sample rate is selectable, relative to SYSCLK by setting register field DAC_CLKDIV. This
field must be set according to the required sampling frequency and depending on the selected
clocking mode (AIF_LRCLKRATE).
In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV.
The DACLRC signal does not automatically match the DAC sample rates; this must be configured
using DACLRC_RATE as described under “Digital Audio Interface Control”.
A clock (OPCLK) derived from SYSCLK can be output on the GPIO pins to provide clocking for other
parts of the system. This clock is enabled by OPCLK_ENA and its frequency is set by OPCLKDIV.
A slow clock (TOCLK) derived from SYSCLK can be used to de-bounce the button/accessory detect
inputs, and to set the timeout period for volume updates when zero-cross detect is used. This clock
is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
The Class D switching amplifier requires a clock; this is derived from SYSCLK via a programmable
divider DCLKDIV.
Table 56 to Table 62 show the clocking and sample rate controls for MCLK input, BCLK output (in
master mode), DACs, class D outputs and GPIO clock output.
The overall clocking scheme for the WM8959 is illustrated in Figure 78.
PRESCALE
f
1
R=f
PLL
2
/f
1
f
2
f/4
f
PLLOUT
SYSCLK_SRC
OPCLKDIV[3:0]
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK /16
1001 – 1111 = Reserved
BCLK_DIV[3:0]
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 44
1111 = SYSCLK / 48
DCLKDIV[2:0]
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
MCLKDIV[1:0]
00 = MCLK
01 = Reserved
10 = MCLK / 2
11 = Reserved
MCLKDIV[1:0]
f/N
OPCLK_ENA
en
TOCLK_ENA
f/N
f/N
f/N
OPCLKDIV
BCLKDIV
[3:0]
SYSCLK
DCLKDIV
Timeout and
De-Bounce
Class D Switching Clock
Clock
DACLRC_RATE
[10:0]
f/N
f/N
DAC_CLKDIV
[2:0]
DAC_CLKDIV2:0]
000 = SYSCLK
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
f/2
f/2
21
19
OUTPUTS
MASTER
TOCLK_RATE
CLOCK
MODE
DAC_SDMCLK_RATE
GPIO Clock Output
Button/accessory detect de-bounce,
Volume update timeout
f/4
256fs
SYSCLK/4
PP, May 2008, Rev 3.1
64fs or
DAC DSP
DACLRC, DACLRC2
BCLK, BCLK2
DAC
Pre-Production
104