WM8959 Wolfson Microelectronics Ltd., WM8959 Datasheet - Page 131

• Manufacturer Part Number: WM8959
• Description: Mobile Multimedia DAC with Dual-mode Class AB/D Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

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Pre-Production
Clocking (2)
R08 (08h)
Audio
Interface (3)
R09 (09h)
Audio
Interface (4)
REGISTER
ADDRESS
14
13
12:11
10
9:5
4:2
1:0
15
14
13
12:0
15
14
13
12
11
BIT
SYSCLK_SRC
CLK_FORCE
MCLK_DIV
[1:0]
MCLK_INV
DAC_CLKDIV
[2:0]
AIF_MSTR1
AIF_MSTR2
AIF_SEL
GPIO1_ENA
AIF_TRIS
DACLRC_DIR
LABEL
0b
0b
00b
0b
00000b
000b
00b
0b
0b
0b
0040h
0b
0b
0b
0b
0b
DEFAULT
SYSCLK Source Select
0 = MCLK
1 = PLL output
Forces Clock Source Selection
0 = Existing SYSCLK source (MCLK or PLL output) must be
active when changing to a new clock source.
1 = Allows existing MCLK source to be disabled before
changing to a new clock source.
SYSCLK Pre-divider. Clock source (MCLK or PLL output) will
be divided by this value to generate SYSCLK.
00 = Divide SYSCLK by 1
01 = Reserved
10 = Divide SYSCLK by 2
11 = Reserved
MCLK Invert
0 = Master clock not inverted
1 = Master clock inverted
Reserved - Do Not Change
DAC Sample Rate Divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2.0
011 = SYSCLK / 3.0
100 = SYSCLK / 4.0
101 = SYSCLK / 5.5
110 = SYSCLK / 6.0
111= Reserved
Reserved - Do Not Change
Audio Interface 1 Master Mode Select
0 = Slave mode
1 = Master mode
Audio Interface 2 Master Mode Select
0 = Slave mode
1 = Master mode
Audio Interface Select
0 = Audio interface 1
1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2,
GPIO5/DACDAT2)
Reserved - Do Not Change
GPIO1 Enable
0 = GPIO1 not enabled
1 = GPIO1 enabled
Reserved - Do Not Change
Audio Interface and GPIO Tristate
0 = Audio interface and GPIO pins operate normally
1 = Tristate all audio interface and GPIO pins
Reserved - Do Not Change
DACLRC Direction
(Forces DACLRC clock to be output in slave mode)
0 = DACLRC normal operation
1 = DACLRC clock output enabled
DESCRIPTION
PP, May 2008, Rev 3.1
WM8959
131