HY29F400A Hynix Semiconductor, HY29F400A Datasheet - Page 18

• Manufacturer Part Number: HY29F400A
• Description: 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
• Manufacturer: Hynix Semiconductor

HY29F400A
all further sector erase data cycles or commands
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a ‘0’, the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
HARDWARE DATA PROTECTION
The HY29F400A provides several methods of pro-
tection to prevent accidental erasure or program-
ming which might otherwise be caused by spuri-
ous system level signals during V
power-down transitions, or from system noise.
These methods are described in the sections that
follow.
Command Sequences
Commands that may alter array data require a
sequence of cycles as described in Table 5. This
provides data protection against inadvertent writes.
Low V
To protect data during V
down, the device does not accept write cycles
when V
18
(Note 4)
Notes:
1. During programming, the program address.
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.
3. Use this path if testing for Program/Erase status.
4. Use this path to test whether sector is in Erase Suspend mode.
NO
During sector erase, an address within any sector scheduled for erasure.
CC
CC
at Valid Address (Note 1)
at Valid Address (Note 1)
Write Inhibit
is less than V
PROGRAM/ERASE
(Note 3)
DQ[6] Toggled?
Read DQ[7:0]
Read DQ[7:0]
COMPLETE
NO
START
LKO
CC
YES
(typically 3.7 volts). The
power-up and power-
Figure 8. Toggle Bit I and II Test Algorithm
CC
NO
NO
EXCEEDED TIME ERROR
power-up and
at Valid Address (Note 1)
PROGRAM/ERASE
DQ[6] Toggled?
Read DQ[7:0]
DQ[5] = 1?
(Note 2)
YES
YES
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
command register and all internal program/erase
circuits are disabled, and the device resets to the
Read mode. Writes are ignored until V
than V
signals to the control pins to prevent unintentional
writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by asserting any one of
the following conditions: OE# = V
WE# = V
must be a logical zero while OE# is a logical one.
IS IN ERASE SUSPEND
SECTOR BEING READ
LKO
DQ[2] Toggled?
IH
Read DQ[7:0]
Read DQ[7:0]
. To initiate a write cycle, CE# and WE#
. The system must provide the proper
YES
CC
is greater than V
NO
IS NOT IN ERASE SUSPEND
SECTOR BEING READ
IL
LKO
, CE# = V
.
Rev. 1.0/Jan. 02
CC
is greater
IH
, or