HY29F800 Hynix Semiconductor, HY29F800 Datasheet - Page 12

• Manufacturer Part Number: HY29F800
• Description: 8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory
• Manufacturer: Hynix Semiconductor

HY29F800
n In a Sector Erase or Chip Erase command se-
n In a Program command sequence, the Read/
n The Read/Reset command may be written be-
Byte/Word Program Command
The host processor programs the device a byte or
word at a time by issuing the Program command
sequence shown in Table 5. The sequence be-
gins by writing two unlock cycles, followed by the
Program setup command and, lastly, a data cycle
specifying the program address and data. This
initiates the Automatic Programming algorithm,
which provides internally generated program
pulses and verifies the programmed cell margin.
The host is not required to provide further con-
trols or timings during this operation. When the
Automatic Programming algorithm is complete, the
device returns to the Read mode. Several meth-
ods are provided to allow the host to determine
the status of the programming operation, as de-
scribed in the Write Operation Status section.
Commands written to the device during execution
of the Automatic Programming algorithm are ig-
nored. Note that a hardware reset immediately
terminates the programming operation. To en-
12
quence, the Read/Reset command may be
written at any time before erasing actually be-
gins, including, for the Sector Erase command,
between the cycles that specify the sectors to
be erased (see Sector Erase command de-
scription). This aborts the command and re-
sets the device to the Read mode. Once era-
sure begins, however, the device ignores Read/
Reset commands until the operation is com-
plete.
Reset command may be written between the
sequence cycles before programming actually
begins. This aborts the command and resets
the device to the Read mode, or to the Erase
Suspend mode if the Program command se-
quence is written while the device is in the
Erase Suspend mode. Once programming
begins, however, the device ignores Read/
Reset commands until the operation is com-
plete.
tween the cycles in an Electronic ID command
sequence to abort that command. As described
above, once in the Electronic ID mode, the
Read/Reset command must be written to re-
turn to the Read mode.
sure data integrity, the aborted program command
sequence should be reinitiated once the reset
operation is complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored “0” to a “1”.
Thus, a bit cannot be programmed from a “0” back
to a “1”. Attempting to do so will set DQ[5] to “1”,
and the Data# Polling algorithm will indicate that
the operation was not successful. A Read/Reset
command or a hardware reset is required to exit
this state, and a succeeding read will show that
the data is still “0”.
Figure 4 illustrates the procedure for the Byte/Word
Program operation.
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by the erase com-
mand, two additional unlock cycles and then the
chip erase data cycle. During chip erase, all sec-
tors of the device are erased except protected
sectors. The command sequence starts the Au-
tomatic Erase algorithm, which preprograms
and verifies the entire memory, except for pro-
tected sectors, for an all zero data pattern prior to
electrical erase. The device then provides the
required number of internally generated erase
pulses and verifies cell erasure within the proper
cell margins. The host system is not required to
N O
Figure 4. Programming Procedure
(See Write Operation Status
Check Programming Status
program Address/Data
C o m m a n d S e q u e n c e :
Last cycle contains
I s s u e P R O G R A M
PROGRAMMING
Last Word/Byte
C O M P L E T E
Section)
START
D o n e ?
Y E S
Normal Exit
DQ[5] Error Exit
ERROR RECOVERY
GO TO
Rev. 4.2/May 01