MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 105
MCIMX35
Manufacturer Part Number
MCIMX35
Description
Manufacturer
Motorola Semiconductor Products
Datasheet
1.MCIMX35.pdf
(132 pages)
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1
2
4.7.21
As SPDIF data is sent using biphase marking code. When encoding, the SPDIF data signal is modulated
to the clock that is twice the bitrate of the data signal.
Figure 81
modulating Rx clock.
STCLK stands for the modulating Tx clock.
Freescale Semiconductor
SPDIFIN Skew: asynchronous inputs, no specs apply
SPDIFOUT output (Load = 50pf)
SPDIFOUT1 output (Load = 30pf)
SRCK period
SRCK high period
SRCK low period
STCLK period
STCLK high period
STCLK low period
SJ11
SJ12
SJ13
• Skew
• Transition Rising
• Transition Falling
• Skew
• Transition Rising
• Transition Falling
On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
V
ID
M -
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
mid point voltage
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
shows the SRCK timing, when SPDIF works in the Rx mode, where SRCK stands for the
SPDIF Timing
Characteristics
Figure 82
Table 69. SJC Timing Parameters (continued)
Preliminary—Subject to Change Without Notice
shows the STCLK timing when SPDIF works in the Tx mode, where
Parameter
Table 70. SPDIF Timing
Symbol
stclkph
srckph
stclkpl
srckpl
stclkp
srckp
—
—
—
—
—
—
—
Min.
40.0
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
—
—
Min.
100
All Frequency
40
—
All Frequencies
Max.
24.2
31.3
13.6
18.0
Max.
0.7
1.5
1.5
—
—
—
—
—
—
44
—
—
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
105