MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 7

• Manufacturer Part Number: MCIMX35
• Manufacturer: Motorola Semiconductor Products

Table 3
2.5
Table 4
modules, see the MCIMX35 reference manual.
Freescale Semiconductor
ARM11 or
ARM1136
Mnemonic
Acronym
1-WIRE
ASRC
Block
•
•
•
•
•
•
•
•
•
ATA
Core
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
Low-interrupt latency
Instruction and data memory management units (MMUs), managed using micro TLB structures
backed by a unified main TLB
Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss
Virtually indexed/physically addressed L1 caches
64-bit interface to both L1 caches
Write buffer (bypassable)
High-speed Advanced Micro Bus Architecture (AMBA)
Vector Floating Point co-processor (VFP) for 3D graphics and other floating-point applications’
hardware acceleration
ETM
summarizes information about the i.MX35 core.
shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the
Module Inventory
1-Wire
interface
Asynchronous
sample rate
converter
ATA module
Block Name
™
ARM1136
Platform
Name
Core
and JTAG-based debug support
The ARM1136™ Platform consists of the ARM1136JF-S core, the ETM
real-time debug modules, a 6 x 5 multi-layer AHB crossbar switch (MAX), and
a Vector Floating Processor (VFP).
The i.MX35 provides a high-performance ARM11 microprocessor core and
highly integrated system functions. The ARM Application Processor (AP) and
other subsystems address the needs of the personal, wireless, and portable
product market with integrated peripherals, advanced processor core, and
power management capabilities.
ARM
SDMA
SDMA
Domain
Preliminary—Subject to Change Without Notice
1
ARM1136
platform
peripherals
peripherals
Connectivity
peripherals
Connectivity
Table 4. Digital and Analog Modules
Subsystem
Table 3. i.MX35 Core
Brief Description
1-Wire provides the communication line to a 1-Kbit Add-Only
Memory. The interface can send or receive 1 bit at a time.
The ASRC is designed to convert the sampling rate of a signal
associated to an input clock into a signal associated to a different
output clock. It supports a concurrent sample rate conversion of
about –120dB THD+N. The sample rate conversion of each channel
is associated to a pair of incoming and outgoing sampling rates.
The ATA block is an AT attachment host interface. Its main use is to
interface with IDE hard disk drives and ATAPI optical disk drives. It
interfaces with the ATA device over a number of ATA signals.
™
L2 interface
Brief Description
Integrated Memory
• 16-Kbyte
• 16-Kbyte data
• 128-Kbyte L2
• 32-Kbyte ROM
• 128-Kbyte RAM
instruction cache
cache
cache
Includes
7