MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 94

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MCIMX35

Manufacturer Part Number
MCIMX35
Description
Manufacturer
Motorola Semiconductor Products
Datasheet

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1
4.7.17.3
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew.
ATA timing parameters.
94
tcable1 cable propagation delay for ata_data
tcable2 cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
tskew1 Max. difference in propagation delay bus clock L-to-H to any of following signals
tskew2 Max. difference in buffer propagation delay for any of following signals
tskew3 Max. difference in buffer propagation delay for any of following signals ata_iordy, ata_data
tskew4 Max. difference in cable propagation delay between ata_iordy and ata_data (read)
tskew5 Max. difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and
tskew6 Max. difference in cable propagation delay without accounting for ground bounce
Name
ti_ds
ti_dh
tbuf
Values provided where applicable.
tsui
tco
tsu
thi
T
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
Bus clock period (ipg_clk_ata)
Set-up time ata_data to ata_iordy edge (UDMA-in only)
hold time ata_iordy edge to ata_data (UDMA-in only)
propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
set-up time ata_data to bus clock L-to-H
set-up time ata_iordy to bus clock H-to-L
hold time ata_iordy to bus clock H to L
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
(read)
Max. buffer propagation delay
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Timing Parameters
Preliminary—Subject to Change Without Notice
Table 61. ATA Timing Parameters
Description
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA2, UDMA3
UDMA0
UDMA1
UDMA4
UDMA5
UDMA5
Freescale Semiconductor
Contributing Factor
Table 61
peripheral clock
transceiver
transceiver
transceiver
frequency
12.0 ns
Value/
5.0 ns
4.6 ns
8.5 ns
8.5 ns
2.5 ns
15 ns
10 ns
cable
cable
cable
cable
cable
7 ns
5 ns
4 ns
7 ns
shows
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