ADSST-21065LKCA-240 STMicroelectronics, ADSST-21065LKCA-240 Datasheet - Page 16

• Manufacturer Part Number: ADSST-21065LKCA-240
• Description: High End/ Multichannel/ 32-Bit Floating-Point Audio Processor
• Manufacturer: STMicroelectronics

SST-Melody-SHARC
OUTPUT DRIVE CURRENT
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ∆V is dependent on the capacitive load, C
load current, I
following equation:
The output disable time t
and t
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. t
and with ∆V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driving.
The output enable time t
signal reaches a high or low voltage level to when the output has
reached a specified high or low trip point, as shown in Figure 4.
If multiple pins (such as the databus) are enabled, the measure-
ment value is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
be the difference between the SST-Melody-SHARC’s output
voltage and the input threshold for the device requiring the hold
time. A typical ∆V will be 0.4 V. C
(per data line), and I
(per data line). The hold time will be t
disable time (i.e., t
DECAY
–100
–120
–20
–40
–60
–80
20
80
60
40
0
0
as shown in Figure 5. The time t
3.1V, +100 C
L
DECAY
3.1V, +85 C
Figure 3. Typical Drive Currents
. This decay time can be approximated by the
0.50
3.3V, +25 C
3.6V, –40 C
DATRWH
DECAY
using the previous equation. Choose ∆V to
L
is the total leakage or three-state current
t
1.00
DECAY
ENA
DIS
V
OL
is calculated with test loads C
3.1V, +100 C
SOURCE VOLTAGE – V
for the write cycle).
is the interval from when a reference
is the difference between t
1.50
=
C
L
3.3V, +25 C
L
2.00
I
× ∆
is the total bus capacitance
L
V
DECAY
OH
V
2.50
MEASURED
3.1V, +85 C
plus the minimum
3.6V, –40 C
3.00
L
is the
MEASURED
3.50
, and the
L
and I
L
,
–16–
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins. The delay and hold specifications given should
be derated by a factor of l.8 ns/50 pF for loads other than the
nominal value of 50 pF. Figure 7 and Figure 8 show how output
rise time varies with capacitance. Figure 9 shows graphically how
output delays and hold vary with load capacitance. (Note that
this graph or derating does not apply to output disable delays; see
the previous section Output Disable time under Test Conditions.)
The graphs of Figures 7, 8, and 9 may not be linear outside the
ranges shown.
REFERENCE
V
V
OH (MEASURED)
OL (MEASURED)
OUTPUT
Figure 7. Typical Rise and Fall Time (10%–90% V
SIGNAL
Figure 6. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Figure 5. Equivalent Device Loading for
AC Measurements (Includes All Fixtures)
18
16
14
12
10
INPUT OR
8
6
4
2
0
OUTPUT
0
t
DIS
TO OUTPUT
OUTPUT STOPS
20
DRIVING
Figure 4. Output Enable
40
PIN
1.5V
t
MEASURED
V
V
50pF
60
OH (MEASURED)
OL (MEASURED)
LOAD CAPACITANCE – pF
t
RISE TIME
DECAY
80
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V.
100
+ V
– V
I
I
OL
OH
120
FALL TIME
OUTPUT STARTS
140
t
ENA
1.0V
2.0V
DRIVING
1.5V
160
1.5V
180
V
V
OH (MEASURED)
OL (MEASURED)
200
REV. 0
DD
)