HY27SS16121M Hynix Semiconductor, HY27SS16121M Datasheet
HY27SS16121M
Related parts for HY27SS16121M
HY27SS16121M Summary of contents
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Document Title 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History No 0.0 Initial Draft 0.1 Renewal Product Group 0.2 Make ...
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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data www.DataSheet4U.com - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC ...
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DESCRIPTION The HYNIX HY27(U/S)SXX121M series is a family of non-volatile Flash memories that use NAND cell technology. The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 ...
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Vcc CE RE NAND www.DataSheet4U.com WE Flash ALE CLE WP Vss Figure 1: Logic Diagram ALE CLE Command Register Rev 0.6 / Oct. 2004 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash I/O8-I/O15, x16 I/O0-I/O7, x8/x16 RB Address ...
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www.DataSheet4U.com NAND ...
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www.DataSheet4U.com Figure 5. 63-FBGA Contactions, x8 Device (Top view through package Figure 6. 63-FBGA Contactions, x16 ...
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MEMORY ARRAY ORGANIZATION The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the ...
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SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Inputs/Outputs (I/O Input/Outputs are used to input the selected address, output the data during ...
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Ready/Busy (RB) The Ready/Busy output, RB open-drain output that can be used to identify if the Program/ Erase/ Read (PER) Controller is currently active. When Ready/Busy is Low, V Ready/Busy goes High, V The use of an open-drain ...
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Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signa- ture and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address ...
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Table 2. Bus Operation BUS Operation Command Input Address Input Data Input Data Output www.DataSheet4U.com Write Protect Standby Note : (1) Only for x16 devices. (2) WP must Table 3: Address Insertion, x8 Devices Bus Cycle I/O ...
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COMMAND SET All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O O and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. ...
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However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A. The pointer operations can also be used before a ...
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Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section. The device defaults to Read A mode after powerup or a Reset operation. Devices, where page0 is read ...
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CLE CE WE www.DataSheet4U.com ALE RE RB 00h/ I/O 01h/ 50h Command Code Note less than 10ns, t ELWL Read A Command, x8 Devices Area A (1st half Page) A9-A25(1) A0-A7 Read B Command, x8 Devices ...
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RB 00h/ I/O 01h/50h Command www.DataSheet4U.com Code Read A Command, x8 Devices Read A Command, x8 Devices Read A Command, x8 Devices Area A Area A Area A Area half Page) ...
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Page Program The Page Program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 ...
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Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster ...
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Once the erase operation has completed the Status Register can be checked for errors. RB I/O 60h www.DataSheet4U.com Block Erase Setup Code Reset The Reset command is used to reset the Command Interface and Status Register. If the Reset command ...
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P/E/R Controller Status Register bit SR6 has two different functions depending on the current operation. During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller ...
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... Part Number HY27US08121M HY27SS08121M HY27US16121M HY27SS16121M Automatic Page 0 Read at Power-Up Automatic Page 0 Read at Power- option available on all devices belonging to the NAND Flash 528 Byte/264 Word Page family. It allows the microcontroller to directly download boot code from page 0, without requiring any command or address input sequence. The Automatic Page 0 Read option is particularly suited for applications that boot from the NAND ...
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Sequential Row Read Disabled If the device is delivered with Sequential row read disabled and Automatic Read Page 0 at Power-up, only the first page (Page 0) will be automatically read after the power-on sequence. Refer to Figure 18. Sequential ...
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Vccth(1) Vcc WE CE www.DataSheet4U.com ALE CLE tBLBH1 (Read Busy time) RB I/O Note: (1 equal to 2.5V for 3.3V Power Supply devices and to 1.5V for 1.8V Power Supply devices. CCth Figure 19. Automatic Page 0 Read ...
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Table 8: Valid Block Symbol N VB PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 9. Rev 0.6 / Oct. 2004 512Mbit ...
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Table 9: Program, Erase Time and Program Erase Endurance Cycles Parameters Page Program Time Block Erase Time Program/Erase Cycles (per block) www.DataSheet4U.com Data Retention MAXIMUM RATING Stressing the device above the ratings listed in Table 10, Absolute Maximum Ratings, may ...
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Table 11: Operating and AC Measurement Conditions Supply Voltage (V www.DataSheet4U.com Ambient Temperature (T Load Capacitance ( TTL GATE and C L Input Pulses Voltages Input and Output Timing Ref. Voltages Note : (1). TBD Table 12: Capacitance ...
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Table 13: DC Characteristics, 3.3V Device and 1.8V Device Sym- Parameter bol I CC1 Operating I Current CC2 www.DataSheet4U.com I CC3 I Stand-by Current (TTL) CC4 Stand-By Current I CC5 (CMOS) I Input Leakage Current LI I Output Leakage Current ...
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Table 14: AC Characteristics for Command, Address, Data Input (3.3V and 1.8V Device) Alt. Symbol Symbol t ALLWL t ALS t ALHWL t CLHWL t CLS t www.DataSheet4U.com CLLWL t t DVWH ELWL CS t WHALH t ...
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Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device) Alt. Sym- Sym- bol bol t t ALLRL1 AR1 Address Latch Low to Read Enable Low t t ALLRL2 AR2 t t Ready/Busy High to Read Enable Low www.DataSheet4U.com ...
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Alt. Sym- Sym- bol bol t t Write Enable High to Read Enable Low WHRL WHR Write Enable Low to Write Enable t t WLWL WC Low Note: (1). The time to Ready depends on the value of the pull-up ...
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CLE tELWL (CE Setup time) CE tWLWH www.DataSheet4U.com WE tALHWL (ALE Setup time) (ALE Hold time) ALE tDVWH (Data Setup time) I/O CLE CE tALLWL (ALE Setup time) ALE tWLWH WE (Data Setup time) I/O Rev 0.6 / Oct. 2004 ...
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CE RE tRLQV www.DataSheet4U.com (RE Accesstime) I/O tBHRL RB Note:1. CLE = Low, ALE = Low High. CLE tCLHWL CE tELWL WE RE (Data Setup time) I/O Rev 0.6 / Oct. 2004 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash ...
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CLE CE WE www.DataSheet4U.com ALE RE I/O 90h Read Electronic Signature Command Note: Refer to table(To see Page 22) for the values of the manufacture and device codes. CLE CE tWHWL WE ALE RE RB I/O 00h or Add.N 01h ...
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CLE CE WE www.DataSheet4U.com ALE RE 50h I/O RB Command Code Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are don't care. 2. Only address cycle 4 is required. Rev 0.6 ...
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CLE CE tWLWL (Write Cycle time) www.DataSheet4U.com WE ALE RE Add. N I/O 80h cycle 1 RB Page Program Setup Code Rev 0.6 / Oct. 2004 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash tWLWL Add. N Add cycle 2 ...
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CLE CE tWLWL (Write Cycle time) WE www.DataSheet4U.com ALE RE Add. N I/O 60h cycle 1 RB Block Erase Setup Command WE ALE CLE RE I/O RB Rev 0.6 / Oct. 2004 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash (Erase Busy ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microprocessor. The only function that was removed ...
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Ready/Busy Signal Electrical Characteristics Figures 32, 33 and 34 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor R can be calculated using the following equation: P www.DataSheet4U.com where I is the sum of the ...
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Figure 36. Resistor Value Waveform Timings for Ready/Busy Signal Rev 0.6 / Oct. 2004 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Vcc=1.8, CL=30pF 400 300 200 1.7 100 0. 1.7 1 Rp(KΩ) Vcc=3.3, CL=100pF 400 ...
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Figure 37. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Table 16: 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Mechanical Data Symbol ...
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Figure 38. 48-WSOP1 - 48-lead Plastic Very Very Thin Small Outline 17mm, Package Outline Table 17: 48-WSOP1 - 48-lead Plastic Thin Small Outline 17mm, Package Mechanical Data Symbol ...
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Figure 39. 63-FBGA - 8.5 x 15mm, 6x8 ball array 0.8mm pitch, Pakage Outline Note: Drawing is not to scale. Table 17: 48-WSOP1 - 48-lead Plastic Thin Small Outline 17mm, Package Mechanical Data Symbol ...
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MARKING INFORMATION Package TSOP1 / WSOP1 www.DataSheet4U.com / FBGA - hynix - KOR - HY27xSxx121mTxB HY: HYNIX 27: NAND Flash x: Power Supply S: Classification xx: Bit Organization 12: Density 1: Mode M: Version x: Package Type x: Package Material ...