HY27US16281A Hynix Semiconductor, HY27US16281A Datasheet - Page 20

no-image

HY27US16281A

Manufacturer Part Number
HY27US16281A
Description
(HY27USxx281A) 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Memory
Manufacturer
Hynix Semiconductor
Datasheet
www.DataSheet4U.com
Rev 0.6 / Nov. 2005
CLE Setup time
CLE Hold time
CE# setup time
CE# hold time
WE# pulse width
ALE setup time
ALE hold time
Data setup time
Data hold time
Write Cycle time
WE# High hold time
Data Transfer from Cell to register
ALE to RE# Delay
CLE to RE# Delay
Ready to RE# Low
RE# Pulse Width
WE# High to Busy
Read Cycle Time
RE# Access Time
RE# High to Output High Z
CE# High to Output High Z
RE# or CE# high to Output hold
RE# High Hold Time
Output High Z to RE# low
CE# Access Time
WE# High to RE# low
Last RE High to busy (at sequential read)
CE# High to Ready (in case of interception by CE# at read)
CE# High Hold Time (at the last serial read)
Device Resetting Time (Read / Program / Erase)
Write Protection time
NOTE:
1. If t
2. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
3. To break the sequential read cycle, CE# must be held for longer time than tCEH.
4. The time to Ready depends on the value of the pull-up resistor tied R/B# pin.ting time.
5. Program / Erase Enable Operation : tWP# high to tWE# High.
Program / Erase Disable Operation : tWP# Low to tWE# High.
CS
is less than 10ns t
WP
must be minimum 35ns, otherwise,
Parameter
Table 12: AC Timing Characteristics
(3)
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
t
WP
may be minimum 25ns.
Symbol
t
t
WW
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WHR
t
t
t
t
t
t
CLH
t
t
t
REA
RHZ
CHZ
REH
t
CRY
CEH
CLS
ALS
ALH
WH
CLR
t
CEA
RST
WP
WC
t
WB
OH
CS
CH
DS
DH
AR
RR
RP
RC
RB
IR
R
(5)
HY27US(08/16)281A Series
Min
25
100
100
10
10
10
20
10
50
15
10
10
20
25
50
10
15
60
0
0
0
0
(1)
3.3Volt
60+tr(R/B#)
5/10/500
Max
100
100
10
30
30
20
45
(2)
(4)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
20

Related parts for HY27US16281A