HY29DL163 Hynix Semiconductor, HY29DL163 Datasheet
HY29DL163
Available stocks
Related parts for HY29DL163
HY29DL163 Summary of contents
Page 1
... Pinout and software compatible with single-power supply Flash devices − Superior inadvertent write protection Preliminary Revision 1.3, June 2001 HY29DL162/HY29DL163 16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory n Data# Polling and Toggle Bits − Provide software confirmation of completion ...
Page 2
... HY29DL162/HY29DL163 GENERAL DESCRIPTION The HY29DL162/HY29DL163 (HY29DL16x Mbit, 3 volt-only CMOS Flash memory orga- nized as 2,097,152 (2M) bytes or 1,048,576 (1M) words. The device is available in 48-pin TSOP and 48-ball FBGA packages. Word-wide data (x16) appears on DQ[15:0] and byte-wide (x8) data appears on DQ[7:0]. The HY29DL16x Flash memory array is organized into 39 sectors in two banks ...
Page 3
... CFI DATA A[19:0], A[-1] TIMER HY29DL162/HY29DL163 DQ[15:0] I/O BUFFERS I/O CONTROL DATA LATCH Y-DECODER Y-GATING 16 Mb FLASH X-DECODER ...
Page 4
... HY29DL162/HY29DL163 PIN CONFIGURATIONS A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[19 A[18] A[17] A[7] A[6] A[5] A[4] A[3] A[2] A[1] 48-Ball FBGA (Top View, Balls Facing Down A[13] A[12 A[9] A[ A[7] A[17 A[3] A[ ...
Page 5
... HY29DL162/HY29DL163 ...
Page 6
... HY29DL162/HY29DL163 CONVENTIONS Unless otherwise noted, a positive logic (active High) convention is assumed throughout this docu- ment, whereby the presence at a pin of a higher, more positive voltage (V ) causes assertion of the IH signal. A ‘#’ symbol following the signal name, e.g., RESET#, indicates that the signal is asserted in the Low state (V ) ...
Page 7
... HY29DL162/HY29DL163 ...
Page 8
... HY29DL162/HY29DL163 Table 2. HY29DL16xB (Bottom Boot Block) Memory Array Organization ...
Page 9
... The host system must drive the CE# and OE# pins Low and drive WE# High for a valid read operation to take place. The BYTE# pin deter- mines whether the device outputs array data in words (DQ[15:0 bytes (DQ[7:0]). HY29DL162/HY29DL163 ...
Page 10
... HY29DL162/HY29DL163 Table 5. HY29DL16x Normal Bus Operations ± ...
Page 11
... WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. r1.3/June 01 HY29DL162/HY29DL163 The “Device Commands” section of this data sheet provides details on the specific device commands implemented in the HY29DL16x. Accelerated Program Operation This device offers improved performance for pro- gramming operations through the ‘ ...
Page 12
... HY29DL162/HY29DL163 The device enters the CE# controlled Deep Standby mode when the CE# and RESET# pins are both held at V ± 0.3V. Note that this more restricted voltage range than V and RESET# are held 0.3V, the device will be in the Normal Standby mode, but the standby current will be greater. ...
Page 13
... Wait 150 us Write 0x40 to Address Wait 1 us Read from Address N O Data = 0x01 Protect Another Figure 1. Sector Group Protect Algorithm HY29DL162/HY29DL163 ...
Page 14
... HY29DL162/HY29DL163 cycle. Also, the unprotect procedure will cause all sectors to become unprotected, thus, sector groups that require protection must be protected again after the unprotect procedure is run. This procedure requires V ID and uses standard microprocessor bus cycle tim- ing to implement sector unprotection. The flow chart in Figure 2 illustrates the algorithm ...
Page 15
... Reset Command Writing the Reset command resets the sectors to the Read or Erase-Suspend mode. Address bits are don’t cares for this command. r1.3/June 01 HY29DL162/HY29DL163 n A read cycle containing a sector address (SA) within the designated bank in A[19:12] and the address 0x04 in A[6:0, A-1] in byte mode, or ...
Page 16
... HY29DL162/HY29DL163 16 ID Electronic 6 r1.3/June 01 ...
Page 17
... The system can access the Sec device by issuing the Enter Sec sequence. The device continues to access the Sec 2 region until the system issues the Exit Sec Region command sequence, which returns the device to normal operation. HY29DL162/HY29DL163 2 region of the 2 Region command 2 17 ...
Page 18
... HY29DL162/HY29DL163 Note: A hardware reset will reset the device to the read array mode. Program Command The system programs the device a word or byte at a time by issuing the appropriate four-cycle Pro- gram command sequence, as shown in Table 10. The sequence begins by writing two unlock cycles, followed by the program setup command and, lastly, the program address and data ...
Page 19
... To ensure that all commands GO TO are accepted recommended that host pro- ERROR RECOVERY cessor interrupts be disabled during the time that HY29DL162/HY29DL163 DQ[5] Error Exit Section) Programming Verified Last Word/Byte ...
Page 20
... HY29DL162/HY29DL163 the additional sector erase commands are being issued and then be re-enabled afterwards. The system can monitor DQ[3] to determine if the 50 µs sector erase time-out has expired, as de- scribed in the Write Operation Status section. If the time between additional sector erase com- mands can be assured to be less than the time- out, the system need not monitor DQ[3] ...
Page 21
... HY29DL162/HY29DL163 ...
Page 22
... HY29DL162/HY29DL163 Two methods are provided for accessing the Elec- tronic ID data. The first requires V pin A[9], as described previously in the Device Operations section. The Electronic ID data can also be obtained by the host through specific commands issued via the command register, as shown in Table 10. This method does not require V ...
Page 23
... HY29DL162/HY29DL163 ...
Page 24
... HY29DL162/HY29DL163 Table 14. CFI Mode: Device Geometry Data Values ...
Page 25
... HY29DL162/HY29DL163 ...
Page 26
... HY29DL162/HY29DL163 obtain valid erase status information on DQ[7]. If all sectors designated for erasing are protected, Data# Polling on DQ[7] is active for approximately 100 µs, then the bank returns to reading array data. When the system detects that DQ[7] has changed from the complement to true data (or “0” to “1” for ...
Page 27
... DQ[ Read DQ[7: Read DQ[7:0] Read DQ[7:0] at Valid Address (Note 1) DQ[6] Toggled DQ[2] Toggled? (Note PROGRAM/ERASE SECTOR BEING READ EXCEEDED TIME ERROR IS IN ERASE SUSPEND HY29DL162/HY29DL163 SECTOR BEING READ IS NOT IN ERASE SUSPEND 27 ...
Page 28
... HY29DL162/HY29DL163 HARDWARE DATA PROTECTION The HY29DL16x provides several methods of pro- tection to prevent accidental erasure or program- ming which might otherwise be caused by spuri- ous system level signals during V power-down transitions, or from system noise. These methods are described in the sections that follow. Command Sequences Commands that may alter array data require a sequence of cycles as described in Table 10 ...
Page 29
... 2 0 Figure 10. Maximum Overshoot Waveform HY29DL162/HY29DL163 ...
Page 30
... HY29DL162/HY29DL163 DC CHARACTERISTICS ...
Page 31
... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note °C. Figure 12. Typical I r1.3/June Time Frequency in MHz Current vs. Frequency CC1 HY29DL162/HY29DL163 3 ...
Page 32
... HY29DL162/HY29DL163 KEY TO SWITCHING WAVEFORMS TEST CONDITIONS 6 Figure 13. Test Setup 3.0 V Input 1.5 V 0.0 V Figure 14. Input Waveforms and Measurement Levels ...
Page 33
... Addresses Stable Figure 15. Read Operation Timings HY29DL162/HY29DL163 ...
Page 34
... HY29DL162/HY29DL163 AC CHARACTERISTICS Hardware Reset (RESET ...
Page 35
... Data Output DQ[14:0] Output DQ[15 Data Output DQ[7:0] Address Input A and t specifications HY29DL162/HY29DL163 ...
Page 36
... HY29DL162/HY29DL163 AC CHARACTERISTICS Program and Erase Operations ...
Page 37
... the true data at the program address. OUT measurement references. It cannot occur as shown during a valid command sequence. Figure 19. Program Operation Timings HY29DL162/HY29DL163 Read Status Data (last two cycles Status ...
Page 38
... HY29DL162/HY29DL163 AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 0x2AA Data 0x55 RY/BY Notes =Sector Address (for sector erase Valid Address for reading status data (see Write Operation Status section the true data at the read address ...
Page 39
... Valid D Valid D IN Read Cycle the data at the read address. OUT HY29DL162/HY29DL163 Valid Valid CE# Controlled Write Cycles Valid PA ...
Page 40
... HY29DL162/HY29DL163 AC CHARACTERISTICS t Addresses DQ[7] DQ[6: RY/BY# Notes Valid Address for reading Data# Polling status data (see Write Operation Status section). 2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle. ...
Page 41
... HY29DL162/HY29DL163 Erase Erase Erase Erase Suspend Suspend Program ...
Page 42
... HY29DL162/HY29DL163 AC CHARACTERISTICS Figure 26. Accelerated Programming Timings RESET# SA, A[6], Don't Care A[1], A[0] Sector Protect/Unprotect Data 0x60 Note: For Sector Group Protect For Sector Unprotect Figure 27. Sector Group Protect and Unprotect Timings ...
Page 43
... HY29DL162/HY29DL163 ...
Page 44
... HY29DL162/HY29DL163 AC CHARACTERISTICS 0x555 for Program 0x2AA for Erase Addresses Data 0xA0 for Program 0x55 for Erase RY/BY RESET# Notes program address program data Valid Address for reading program or erase status (see Write ...
Page 45
... 11.90 12.10 25 18.30 18.50 19.80 20. 0.50 0.70 HY29DL162/HY29DL163 ...
Page 46
... HY29DL162/HY29DL163 PACKAGE DRAWINGS Physical Dimensions FBGA48 - 48-Ball Fine-Pitch Ball Grid Array (measurements in millimeters) Note: Unless otherwise specified, tolerance = ± 0.20 MIN Ø 0.30 ± 0.05 46 9.00 ± 0.10 1.80 ± 0.10 C 5.60 BSC 0. Ø 0. Ø 0.08 ...
Page 47
... HY29DL162/HY29DL163 ° ° ...
Page 48
... HY29DL162/HY29DL163 © 2001 by Hynix Semiconductor America. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Hynix Semiconductor Inc. or Hynix Semiconductor America (collec- tively “Hynix”). The information in this document is subject to change without notice ...