MT54V1MH18A Micron Semiconductor Products, Inc., MT54V1MH18A Datasheet - Page 3

• Manufacturer Part Number: MT54V1MH18A
• Description: 18Mb QDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Programmable Impedance Output
Buffer
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
resistor must be five times the desired impedance. For
example, a 350 W resistor is required for an output
impedance of 70 W . To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175 W to 350 W . Alternately, the ZQ ball
can be connected directly to V
the device in a minimum impedance mode.
because variations may occur in supply voltage and
temperature over time. The device samples the value
of RQ. Impedance updates are transparent to the sys-
tem; they do not affect device operation, and all data
sheet timing and current specifications are met during
an update.
set at 50 W . To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
Clock Considerations
loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.
18Mb: 2.5V V
MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03
The QDR SRAM is equipped with programmable
Output impedance updates may be required
The device will power up with an output impedance
This device does not utilize internal phase-locked
DD
, HSTL, QDRb2 SRAM
DD
Q, which will place
SS
. The value of the
3
It is strontly recommended that the clocks operate for
a number of cycles prior to initiating commands to the
SRAM. This delay permits transmission line charging
effects to be overcome and allows the clock timing to
be nearer to its steady-state value.
Single Clock Mode
pair by tying C and C# HIGH. In this mode the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.
Depth Expansion
write ports. This allows for easy depth expansion. Both
port selects are sampled on the rising edge of K only.
Each port can be independently selected and dese-
lected and does not affect the operation of the oppo-
site port. All pending transactions are completed prior
to a port deselecting.
The SRAM can be used with the single K, K# clock
The output echo clocks are precise references to
Port select inputs are provided for the read and
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
1 MEG x 18, 512K x 36
, HSTL, QDRb2 SRAM
©2003 Micron Technology, Inc.