MT54V1MH18E Micron Semiconductor Products, Inc., MT54V1MH18E Datasheet - Page 10

• Manufacturer Part Number: MT54V1MH18E
• Description: 18Mb QDR SRAM, 2.5V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 5:
Notes 1–8
Table 6:
Notes 9, 10
NOTE:
18Mb: 2.5V V
MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. ­ means rising edge; ¯ means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C
3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the ris-
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification. A0 refers to the initial address input during a WRITE or
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by
7. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation; however,
8. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecu-
9. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation,
10.This table illustrates operation for x18 devices. The x36 device operation is similar except for the addition of BW2#
OPERATION
OPERATION
WRITE Cycle:
Load address, input write data on
two consecutive K and K# rising
edges
READ Cycle:
Load address, output data on two
consecutive C and C# rising edges
NOP: No operation
STANDBY: Clock stopped
WRITE D0–17 at K rising edge
WRITE D0–17 at K# rising edge
WRITE D0–8 at K rising edge
WRITE D0–8 at K# rising edge
WRITE D9–17 at K rising edge
WRITE D9–17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
and C# are HIGH, then data outputs are delivered at K and K# rising edges.
ing edge of K.
READ cycle. A0+1 refers to the next internal burst address in accordance with the burst sequence.
overcoming transmission line charging symmetrically.
it is strongly recommended that this signal is brought HIGH, as shown in the truth table.
tive K clock rising edges is not permitted. The device will ignore the second request.
provided that the setup and hold requirements are satisfied.
(controls D18:D26) and BW3# (controls D27:D35).
DD
, HSTL, QDRb4 SRAM
Truth Table
BYTE WRITE Operation
Stopped
L®H
L®H
L®H
K
R#
X
H
X
L
W#
X
H
X
L
10
Q = High-Z
Previous
Q
D or Q
D
2.5V V
C#(t)­
D = X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
K(t)­
State
A
A
at
at
(A0)
(A0)
L®H
L®H
L®H
L®H
K
DD
Q = High-Z
D
Q
1 MEG x 18, 512K x 36
K#(t + 1)­
C(t + 1)­
Previous
A
A
D or Q
D = X
(A0 + 1)
State
(A0 + 1)
, HSTL, QDRb4 SRAM
at
at
L®H
L®H
L®H
L®H
K#
Q
Q = High-Z
D
C#(t + 2)­
Previous
K(t+ 2)­
A
A
D or Q
D = X
(A0 + 2)
(A0 + 2)
State
at
at
BW0#
0
0
0
0
1
1
1
1
©2003 Micron Technology, Inc.
Q = High-Z
D
Q
K#(t + 3)­
C(t + 3)­
Previous
A
A
D or Q
D = X
(A0 + 3)
State
(A0 + 3)
BW1#
at
at
0
0
1
1
0
0
1
1