MT54V1MH18E Micron Semiconductor Products, Inc., MT54V1MH18E Datasheet - Page 2

• Manufacturer Part Number: MT54V1MH18E
• Description: 18Mb QDR SRAM, 2.5V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port
operation.
trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte write or nibble
write selection. Write data and byte writes are regis-
tered on the rising edges of both K and K#. The
addressing within each burst of four is fixed and
sequential, beginning with the lowest and ending with
the highest address. All synchronous data outputs pass
through output registers controlled by the rising edges
of the output clocks (C and C# if provided, otherwise K
and K#).
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.
sramds) for the latest data sheet.
READ/WRITE Operations
burst of four data, requiring two full clock cycles of bus
utilization. Any request that attempts to interrupt a
burst-in-progress is ignored. The resulting benefit is
that the address rate is kept down to the clock fre-
quency even when both buses are 100 percent utilized.
18Mb: 2.5V V
MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03
Depth expansion is accomplished with port selects
All synchronous inputs pass through registers con-
Four balls are used to implement JTAG test capabili-
The SRAM operates from a 2.5V power supply, and
Please refer to Micron’s Web site
All bus transactions operate on an uninterruptable
DD
, HSTL, QDRb4 SRAM
(www.micron.com/
2
by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of K, using C and C# as the
output timing references, or using K and K# if C and C#
are tied HIGH. If C and C# are tied HIGH, they may not
be toggled during device operation. Output tri-stating
is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex output enable
(OE) timing generation. Back-to-back READ cycles are
initiated every second K rising edge. Any command in
between is ignored, since the burst sequence may not
be interrupted and requires two full clock cycles.
edge. Data is expected at both rising edges of K and K#,
beginning one clock period later. Write registers are
incorporated to facilitate pipelined self-timed WRITE
cycles and provide fully coherent data for all combina-
tions of reads and writes. A read can immediately fol-
low a write even if they are to the same address.
Although the write data has not been written to the
memory array, the SRAM will deliver the data from the
write register instead of using the older data from the
memory array. The latest data is always utilized for all
bus transactions. WRITE cycles are initiated every sec-
ond K rising edge. Any command is ignored, since the
burst sequence may not be interrupted.
BYTE WRITE Operations
LOW byte write controls are registered coincident with
their corresponding data. This feature can eliminate
the need for some READ-MODIFY-WRITE cycles, col-
lapsing it to a single BYTE WRITE operation in some
instances.
READ cycles are pipelined. The request is initiated
WRITE cycles are initiated by W# LOW at K rising
BYTE WRITE operations are supported. The active
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
1 MEG x 18, 512K x 36
, HSTL, QDRb4 SRAM
©2003 Micron Technology, Inc.