MPC5534 Frescale, MPC5534 Datasheet
MPC5534
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MPC5534 Summary of contents
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... Freescale Semiconductor Product Brief MPC5534 Microcontroller Product Brief The MPC5534 MCU is the third member of the family of next generation microcontrollers based on the TM www.DataSheet4U.com PowerPC Book E architecture. This family of parts contains many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family ...
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... External Bus Interface has been designed to support most of the standard memories used with the MPC5xx family. The MPC5534 does not support arbitration between itself and other masters on the external bus. It must be either the only master on the external bus or act as a slave-only device. ...
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... Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard • Device/board test support per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator controller for regulating 3.3V down to 1.5V for core logic www.DataSheet4U.com Freescale Semiconductor MPC5534 Microcontroller Product Brief, Rev. 0.0 3 www.DataSheet www.DataSheet www.DataSheet www.DataSheet4U 4U.com ...
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... Block Diagram 1 Block Diagram Figure 1 shows a top-level block diagram of the MPC5534. 1.5V Regulator Control FMPLL Nexus Interface eDMA channels www.DataSheet4U.com Slave Flash 1 Mbyte Peripheral Bridge A (PBRIDGE_A) eTPU 32 channel MPC5500 Device Module Acronyms CAN – Controller area network (FlexCAN) DSPI – Deserial/serial peripheral interface DMA – ...
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... CAN_E No 2 DSPI_A No DSPI_B No DSPI_C Yes DSPI_D Yes 0 channel 32 channel eTPU_A Yes eTPU_B No Code memory 12k MPC5534 Microcontroller Product Brief, Rev. 0.0 MPC5500 Family Comparison e200z3 e200z6 e200z6 Yes No No None 8k 32k 1 2 Unified Unified 16 entry 32 entry 32 entry 4x5 4x5 3x5 Class 3+ ...
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... May not be externally available in some package configurations. 6 The FEC signals are shared with Data Bus pins DATA[16:31]. www.DataSheet4U.com 3 MPC5534 Features List This section provides a high-level description of the features found on the MPC5534. 3.1 Operating Parameters • Fully static operation, 0 MHz - 80 MHz • -40° to 150° C junction temperature (125° C ambient temperature) • ...
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... Memory interface support for saving and restoring two registers per cycle • Thirty-two 64-bit general purpose registers (GPRs) • Memory management unit (MMU) with 16-entry fully-associative translation look-aside buffer (TLB) Freescale Semiconductor CMOS switch levels (with hysteresis) DDE MPC5534 Microcontroller Product Brief, Rev. 0.0 MPC5534 Features List 7 www.DataSheet www.DataSheet4U www.DataSheet www.DataSheet 4U.com 4U 4U ...
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... Supports variable sized queues and circular queues • Source and destination address registers are independently configured to post-increment or remain constant • Each transfer is initiated by a peripheral, CPU, or eDMA channel request 8 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www.DataSheet www.DataSheet4U 4U.com ...
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... PLL normal mode with crystal reference (default) — PLL normal mode with external oscillator reference — PLL dual controller mode for EXTAL to CLKOUT skew minimization • Programmable frequency modulation Freescale Semiconductor MPC5534 Microcontroller Product Brief, Rev. 0.0 MPC5534 Features List 9 www.DataSheet www.DataSheet4U www.DataSheet www ...
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... Configurable wait states • Optional automatic CLKOUT gating to save power and reduce EMI • Compatible with MPC5xx external bus (with some limitations) 10 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www.DataSheet www.DataSheet4U 4U.com 4U 4U ...
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... Power-on reset support — Reset status register provides last reset source to software — Glitch detection on reset input — Software controlled reset assertion • External interrupt Freescale Semiconductor MPC5534 Microcontroller Product Brief, Rev. 0.0 MPC5534 Features List 11 www.DataSheet www.DataSheet4U www.DataSheet www.DataSheet 4U.com ...
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... Configurable access timing allowing use in a wide range of system frequencies. • Multiple-mapping support and mapping-based block access timing (0–31 additional cycles) allowing use for emulation of other memory types. 12 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www.DataSheet www.DataSheet4U 4U.com ...
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... Supports serial bootloading of either PowerPC Book E code (default) or VLE code • Supports censorship protection for internal Flash memory • Provides an option to enable the core watchdog timer 3.14 Enhanced modular I/O system (eMIOS) • 24 unified channels Freescale Semiconductor MPC5534 Microcontroller Product Brief, Rev. 0.0 MPC5534 Features List 13 www.DataSheet www.DataSheet4U www.DataSheet www.DataSheet 4U.com 4U 4U ...
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... Shared time or angle counter bus (STAC) for all eTPU and eMIOS channels • DMA and interrupt request support • Nexus Class 3 Debug support (with some Class 4 support) 3.16 Enhanced queued A/D converter (eQADC) • Two independent ADCs 14 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www.DataSheet www.DataSheet4U 4U.com 4U 4U ...
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... Supports configurable digital filter • Supports 4 external 8-to-1 muxes which can expand the input channels 3.17 Deserial serial peripheral interface module (DSPI) • 3 DSPI modules • SPI Freescale Semiconductor MPC5534 Microcontroller Product Brief, Rev. 0.0 MPC5534 Features List 15 www.DataSheet www.DataSheet4U www.DataSheet www.DataSheet 4U.com 4U 4U ...
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... Two receiver wake-up methods, idle line and address mark • Interrupt-driven operation with flags • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection • 2 channel eDMA interface 16 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www.DataSheet www.DataSheet4U 4U.com 4U 4U .com .com .com ...
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... Real time development support for e200z3 core and eTPU engine through Nexus Class 3 (selected Class 4 support) • Read and write access — Run-time access of entire memory map Freescale Semiconductor MPC5534 Microcontroller Product Brief, Rev. 0.0 MPC5534 Features List 17 www.DataSheet www.DataSheet4U www.DataSheet www.DataSheet 4U ...
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... MPC5534 Memory Map This section describes the MPC5534 memory map. All addresses in the device, including those that are reserved, are identified in the tables. The addresses represent the physical addresses assigned to each IP block. Logical addresses are translated by the MMU into physical addresses. ...
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... N N N/A 192 N/A MPC5534 Microcontroller Product Brief, Rev. 0.0 MPC5534 Memory Map Emulation mapping of Flash Array 2 External Memory SRAM Array, Standby Powered SRAM Array Reserved Reserved Bridge A Registers Reserved FMPLL Flash Configuration Reserved System Integration Unit (SIU) Reserved ...
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... External Master Mode Operation Memory Map When the MPC5534 MCU acts as a slave from an external master device, the External Bus Interface (EBI) translates the 24-bit external address to a 32-bit internal address. Table 3. External to Internal Memory Map Translation Table for Slave Mode ...
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... Table 4 shows the memory map for a MPC5534 MCU acting as a slave from the point of view of the external master. Table 4. MPC5534 Slave Memory Map as seen from an External Master External Address Range 0x00_0000 0x80_0000 - 0x8F_FFFF 0x90_0000 - 0xBF_FFFF 0xC0_0000 - 0xC0_FFFF 0xC1_0000 - 0xCF_FFFF 0xD0_0000 - 0xCF_FFFF ...
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... This results in a significantly smaller code size footprint without affecting performance noticeably. The e200z3 core supports both the PowerPC Book E and VLE instruction sets. 22 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www ...
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... The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the Freescale Semiconductor MPC5534 Microcontroller Product Brief, Rev. 0.0 Detailed Features 23 www.DataSheet www ...
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... The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O 24 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www ...
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... ECC handling is done on a 32-bit boundary and is completely software compatible with MPC5500 family devices with an e200z6 core and 64-bit wide ECC syndrome. Because the e200z3 core in MPC5534 is a cacheless processor, the platform RAM is organized on a 32-bit boundary versus the 64-bit organization used on other MPC5500 family MCUs based on the e200z6 core ...
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... Both time bases can be exported to the eMIOS timer module — Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time. 26 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www.DataSheet www ...
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... The eQADC provides a parallel interface to two on-chip analog to digital converters (ADCs), and a single master to single slave serial interface to an off-chip external device. The two on-chip ADCs are designed to allow access to all the analog channels. Freescale Semiconductor MPC5534 Microcontroller Product Brief, Rev. 0.0 Detailed Features Section 5.18, “Nexus,” for 27 www ...
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... FlexCAN The MPC5534 MCU contains two controller area network (FlexCAN) blocks. Each FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used pimarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth ...
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... MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several individual Nexus blocks that are selected to provide the development support interface for the MPC5534. The NDI block interfaces to the host processor, eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003 standard. The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the MCUs internal memory map and access to the core and eTPU internal registers during halt ...
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... IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 standard. 6 Chip Configuration Various functions of the MPC5534 may be implemented at reset. The following operations may be configured: • Boot mode 30 MPC5534 Microcontroller Product Brief, Rev ...
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... Watchdog timer enable 7 Documentation Table 5 lists other documents that provide information related to the MPC5534 and its development support tools. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com. ...
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... Documentation www.DataSheet4U.com 32 MPC5534 Microcontroller Product Brief, Rev. 0.0 Freescale Semiconductor www.DataSheet www.DataSheet www.DataSheet www.DataSheet4U 4U.com 4U 4U .com .com .com ...
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... Semiconductor, Inc. All other product or service names are the property of their respective owners. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. © Freescale Semiconductor, Inc. 2005. All rights reserved. MPC5534PB Rev. 0.0 11/2005 www.DataSheet www.DataSheet www ...