MPC5534 Frescale, MPC5534 Datasheet - Page 27
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MPC5534
Manufacturer Part Number
MPC5534
Description
Microcontroller
Manufacturer
Frescale
Datasheet
1.MPC5534.pdf
(33 pages)
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5.14 eQADC
The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions
for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital
converters (ADCs), and a single master to single slave serial interface to an off-chip external device. The
two on-chip ADCs are designed to allow access to all the analog channels.
Freescale Semiconductor
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— Both timebases visible from the host
Event-triggered microengine:
— Fixed-length instruction execution in two-system-clock microcycle
— 12 Kbytes of code memory (SCM)
— 2.5 Kbytes of parameter (data) RAM (SPRAM)
— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in
— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and
— Additional 24 bit Multiply/MAC/Divide unit which supports all signed/unsigned
Resource sharing features support channel use of common channel registers, memory and
microengine time:
— Hardware scheduler works as a “task management” unit, dispatching event service routines by
— Automatic channel context switch when a "task switch" occurs, i.e., one function thread ends
— SPRAM shared between host CPU and eTPU, supporting communication either between
— Hardware implementation of 4 semaphores support coherent parameter sharing between both
— Dual-parameter coherency hardware support allows atomic access to two parameters by host
Test and development support features:
— Nexus Class 3 debug, supporting single-step execution, arbitrary microinstruction execution,
— Software breakpoints
— SCM continuous signature-check built-in self test (MISC - multiple input signature
selected combinations
subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands,
single bit manipulation, shift operations, sign extension and conditional execution
Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in
parallel with the regular microcode commands
pre-defined, host-configured priority.
and another begins to service a request from other channel: channel-specific registers, flags
and parameter base address are automatically loaded for the next serviced channel
channels and host or inter-channel
eTPU engines
hardware breakpoints and watchpoints on several conditions (see
more details on the Nexus module)
calculator), runs concurrently with eTPU normal operation
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MPC5534 Microcontroller Product Brief, Rev. 0.0
Section 5.18,
Detailed Features
“Nexus,” for
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