MPC5534 Frescale, MPC5534 Datasheet - Page 30

• Manufacturer Part Number: MPC5534
• Description: Microcontroller
• Manufacturer: Frescale

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Chip Configuration
5.19 JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan
technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC
block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001
standard.
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Various functions of the MPC5534 may be implemented at reset. The following operations may be
configured:
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— Subset of PowerPC Book E software debug facilities with OnCE block (Nexus Class 1
eTPU development support features
— IEEE-ISTO 5001-2003 standard Class 3 compliant for the eTPU
— Data trace via data write messaging and data read messaging. This allows the development
— Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by
— Program trace via branch trace messaging. BTM displays program flow discontinuities (start,
— Watchpoint messaging via the auxiliary port. WPM provides visibility of the occurrence of the
— Nexus based breakpoint/watchpoint configuration and single step support.
Run-time access to the on-chip memory map via the Nexus read/write access protocol. This
feature supports accesses for run-time internal visibility, calibration variable acquisition,
calibration constant tuning, and external rapid prototyping for powertrain automotive
development systems.
All features are independently configurable and controllable via the IEEE 1149.1 I/O port.
The NDI block reset is controlled with JCOMP, power-on reset, and the TAP state machine. All
these sources are independent of system reset.
Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
Boot mode
Chip Configuration
features implemented by OnCE)
tool to trace reads and writes to selected shared parameter RAM (SPRAM) address ranges.
Four data trace windows are available.
providing visibility of which channel is being serviced. An ownership trace message is
transmitted to indicate when a new channel service request is scheduled, allowing the
development tools to trace task flow. A special OTM is sent when the engine enters in idle
state, meaning that all requests were serviced and no new requests are yet scheduled.
repeat, jump, return, etc.), allowing the development tool to interpolate what transpires
between the discontinuities. Thus static code may be traced. The branch trace messaging
method uses the branch/predicate method to reduce the number of generated messages.
eTPUs’ watchpoints and breakpoints.
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MPC5534 Microcontroller Product Brief, Rev. 0.0
Freescale Semiconductor
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