MT9315 Zarlink Semiconductor, MT9315 Datasheet - Page 2

• Manufacturer Part Number: MT9315
• Description: Acoustic Echo CANceller
• Manufacturer: Zarlink Semiconductor

Features
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Sin
MD1
MD2
Rout
Contains two echo cancellers: 112ms acoustic
echo canceller + 16ms line echo canceller
Works with low cost voice codec. ITU-T G.711
or signed mag /A-Law, or linear 2’s comp
Each port may operate in different format.
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Fast re-convergence time: tracks changing
echo environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for exceptional performance in high
background noise environments
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled
oscillation in high loop gain conditions
Offset nulling of all PCM channels
Serial micro-controller interface
ST-BUS or variable-rate SSI PCM interfaces
User gain control provided for speaker path
(-24dB to +21dB in 3dB steps)
AGC on speaker path
VDD
Linear
/A-Law/
L
/A-Law
inear/
VSS
NBSD
Offset
Null
PWRDN
Limiter
S
Adaptive
1
Filter
AGC
+
Figure 1 - Functional Block Diagram
FORMAT
+
-24 -> +21dB
R
-
3
User
Gain
S
2
ENA2
CONTROL
UNIT
Detector
Double
Talk
ADV
NLP
ADV
NLP
DS5038
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Applications
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ENA1
R
Limiter
2
Handles up to 0 dB acoustic echo return loss
and 0dB line ERL
Transparent data transfer and mute options
20 MHz master clock operation
Low power mode during PCM Bypass
Full duplex speaker-phone for digital telephone
Echo cancellation for video conferencing
Handsfree in automobile environment
Full duplex speaker-phone for PC
S
3
MT9315AP
MT9315AE
-
Adaptive
+
LAW
Filter
R
+
1
Ordering Information
Acoustic Echo Canceller
F0i
-40 C to + 85 C
NBSD
Interface
Controller
Micro
Howling
BCLK/C4i
Advance Information
Offset
ISSUE 3
Null
CMOS
Linear/
/A-Law
28 Pin PLCC
28 Pin PDIP
MCLK
Linear
/A-Law/
MT9315
February 1999
DATA2
DATA1
Sout
SCLK
CS
Rin
1