MT9315 Zarlink Semiconductor, MT9315 Datasheet - Page 3

• Manufacturer Part Number: MT9315
• Description: Acoustic Echo CANceller
• Manufacturer: Zarlink Semiconductor

MT9315
Pin Description
2
10, 11
Pin #
12
1
2
3
4
5
6
7
8
9
Name
MCLK
ENA1
ENA2
MD1
MD2
LAW
VSS
Rin
Sin
IC
IC
FORMAT
PWRDN
MCLK
ENA1
ENA2
LAW
MD1
MD2
VSS
Rin
Sin
IC
IC
IC
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input). This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this strobe must be present for frame synchronization. This is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for on Rin/Sout pins.
Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the MD1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description).
ST-BUS Mode for Rin/Sout (Input). When in ST-BUS mode, this pin, in conjunction with the
ENA1 pin, will select the proper ST-BUS mode for Rin/Sout pins (see ST-BUS Operation
description). Connect this pin to Vss in SSI mode.
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input).This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the MD2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description).
ST-BUS Mode for Sin/Rout (Input).When in ST-BUS mode, this pin in conjunction with the
ENA2 pin, will select the proper ST-BUS mode for Sin/Rout pins (see ST-BUS Operation
description). Connect this pin to Vss in SSI mode.
Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2’s complement linear format. This is the Receive Input
channel from the line (or line) side. Data bits are clocked in following SSI or ST-BUS timing
requirements.
Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may
be in either companded or 2’s complement linear format. This is the Send Input channel (from
the microphone). Data bits are clocked in following SSI or ST-BUS timing requirements.
Digital Ground: Nominally 0 volt.
Master Clock (Input): Nominal 20 MHz Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock source.
Internal Connection (Input): Must be tied to Vss.
Internal Connection (Input). Tie to Vss.
A/ Law Select (Input). When low, selects
Law companded PCM. This control is for both serial pcm ports.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
PDIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
F0i
IC
IC
BCLK/C4i
Rout
Sout
VDD
NC
DATA1
DATA2
SCLK
NC
NC
CS
Figure 2 - Pin Connections
Description
MCLK
VSS
Rin
Sin
Law companded PCM. When high, selects A-
IC
IC
IC
5
6
7
8
9
10
11
PLCC
Advance Information
25
24
23
22
21
20
19
F0i
Rout
Sout
VDD
NC
DATA1
DATA2