MT9315 Zarlink Semiconductor, MT9315 Datasheet - Page 4

• Manufacturer Part Number: MT9315
• Description: Acoustic Echo CANceller
• Manufacturer: Zarlink Semiconductor

Advance Information
Pin Description (continued)
Notes:
1. All inputs have TTL compatible logic levels except for MCLK, Sin and Rin pins which have CMOS compatible logic levels and PWRDN
2. All outputs are CMOS pins with CMOS logic levels except DATA1 which is TTL bidirectional.
Glossary
Double-Talk
Near-end Single-Talk
Far-end Single-Talk
ADV NLP
Howling
Narrowband
NBSD
Noise-Gating
Offset Nulling
Reverberation time
ERL
ERLE
AGC
15, 16
27, 28
Pin #
pin which has Schmitt trigger compatible logic levels.
13
14
17
18
19
20
21
22
23
24
25
26
BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit
FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects
PWRDN Power-down (Input). An active low resets the device and puts the MT9315 into a low-power
DATA2
DATA1
Name
SCLK
VDD
Rout
Sout
NC
CS
NC
F0i
IC
ITU-T (G.711) PCM code. This control is for both serial pcm ports.
stand-by mode.
No Connect (Output). This pin should be left un-connected.
Serial Port Synchronous Clock (Input). Data clock for the serial microport interface.
Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low.
Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin
is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and
must be tied to Vss or Vdd.
Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1
pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for
transmitting and receiving data.
No Connect (Output). This pin should be left un-connected.
Positive Power Supply. Nominal is 5V
Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream. Data
may be in either companded or 2’s complement linear PCM format. This is the Send Out
signal after acoustic echo cancellation and Non-linear processing. Data bits are clocked out
following SSI or ST-BUS timing requirements.
Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2’s complement linear PCM format. This is the Receive
out signal after line echo cancellation Non-linear processing, AGC, and gain control. Data bits
are clocked out following SSI or ST-BUS timing requirements.
Frame Pulse (Input). In ST-BUS operation, this is an active-low frame alignment pulse. SSI
operation is enabled by connecting this pin to Vss.
clock. This clock must be synchronous with ENA1, and ENA2 enable strobes.
In ST-BUS operation, C4i pin must be connected to the 4.096MHz (C4) system clock.
Internal Connection (Input). Tie to Vss.
Simultaneous signals present on Rin and Sin.
Signals only present at Sin input.
Signals only present at Rin input.
Advanced Non-Linear-Processor
Oscillation caused by feedback from acoustic and line echo paths
Any mono or dual sinusoidal signals
Narrow Band Signal Detector
Audible switching of background noise
Removal of DC component
The time duration before an echo level decays to -60dBm
Echo Return Loss
Echo Return Loss Enhancement
Automatic Gain Control
Description
MT9315
3