MT8920BC Zarlink Semiconductor, MT8920BC Datasheet - Page 12

• Manufacturer Part Number: MT8920BC
• Description: MT8920 - 32 Channels TDM (ST-BUS) to Parallel Bus Access Circuit
• Manufacturer: Zarlink Semiconductor

MT8920B
12
connected
appropriately.
In order to facilitate efficient use of the parallel bus
another signal, similar to STCH, is supplied by the
STPA.
for the last half of each channel (Figure 19). This
may be connected to a second STPA, residing on the
same physical parallel bus, enabling it to perform its
read/write operations in the second half of each
channel.
Figure 9 - "Daisy-chained" STPA’s in 32 Channel
Parallel Bus Controller Mode (Mode 3)
Common Bus
Data Bus
Address
ST-BUS
Delayed Chip Select (DCS) becomes active
STCH
DCS
This allows a large number of devices,
WE
C4i
OE
directly
BIT 7
to CS to enable the device
A0
A1
A2
A3
A4
OE
WE
A0
A1
A2
A3
A4
OE
WE
Figure 10 - Timing Relationship for Mode 3 Daisy Chaining
MMS MS1 24/32
MMS MS1 24/32
N + 1
0
0
CS
CS
BIT 6
IN
0
0
STCH
1
1
DCS
BIT 5
STi0
STo0
STi0
STo0
OUT
N - 1
CHANNEL N
BIT 4
connected on a common bus, to be driven by two
ST-BUS streams. Figure 9 shows how this "daisy
chaining" of STPA’s is implemented while Figure 10
illustrates the timing on the shared parallel bus.
Applications
Parallel PBX to Digital Trunk Interface
The STPA is an ideal component for interfacing
parallel PBX environments to Zarlink’s family of
digital trunk devices.
Figure 11 shows a typical interface for both T1/ESF
and CRC-4 CEPT digital trunks to a system utilizing
a parallel bus architecture.
T1/ESF and the MH89790B CRC-4 CEPT trunk
modules are shown interfaced to a parallel bus
structure using two STPAs operating in modes 1 and
2.
The first STPA operating in mode 2
MS1=1,
information between the parallel telecom bus and the
T1 or CEPT link via DSTi and DSTo. The second
STPA, operating in mode 1 (MMS=1) provides
access from the signalling and link control bus to the
MH89760B
channels. All signalling and link functions may be
controlled easily through the STPA transmit RAM’s
Tx0, Tx1, while status information is read at receive
RAM Rx0. In addition, interrupts can be set up to
notify the system in case of slips, loss of sync,
alarms, violations, etc.
BIT 3
N + 1
24/32=0),
IN
BIT 2
or
MH89790B
BIT 1
routes
OUT
N - 1
BIT 0
data
status
Both the MH89760B
Data Sheet
and/or
and
(MMS=0,
control
voice